23 #define DISP_REG_OVL_INTEN			0x0004
25 #define DISP_REG_OVL_INTSTA			0x0008
26 #define DISP_REG_OVL_EN				0x000c
27 #define DISP_REG_OVL_RST			0x0014
28 #define DISP_REG_OVL_ROI_SIZE			0x0020
29 #define DISP_REG_OVL_DATAPATH_CON		0x0024
30 #define OVL_LAYER_SMI_ID_EN				BIT(0)
33 #define DISP_REG_OVL_ROI_BGCLR			0x0028
34 #define DISP_REG_OVL_SRC_CON			0x002c
35 #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
36 #define DISP_REG_OVL_SRC_SIZE(n)		(0x0038 + 0x20 * (n))
37 #define DISP_REG_OVL_OFFSET(n)			(0x003c + 0x20 * (n))
38 #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
40 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
42 #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
43 #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
44 #define DISP_REG_OVL_ADDR_MT2701		0x0040
45 #define DISP_REG_OVL_CLRFMT_EXT			0x02d0
46 #define OVL_CON_CLRFMT_BIT_DEPTH_MASK(n)		(GENMASK(1, 0) << (4 * (n)))
48 #define OVL_CON_CLRFMT_8_BIT				(0)
50 #define DISP_REG_OVL_ADDR_MT8173		0x0f40
51 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
52 #define DISP_REG_OVL_HDR_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x04)
53 #define DISP_REG_OVL_HDR_PITCH(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x08)
78 					0 : OVL_CON_CLRFMT_RGB)
80 					OVL_CON_CLRFMT_RGB : 0)
82 #define	OVL_CON_ALPHA		0xff
175 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);  in mtk_disp_ovl_irq_handler()
207 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
215 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
264 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
271 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
284 	mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,  in mtk_ovl_set_afbc()
312 	if (w != 0 && h != 0)  in mtk_ovl_config()
323 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
324 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
358 	return 0;  in mtk_ovl_layer_check()
369 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
391 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
393 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
493 	unsigned int pitch_lsb = pending->pitch & GENMASK(15, 0);  in mtk_ovl_layer_config()
499 	unsigned int ignore_pixel_alpha = 0;  in mtk_ovl_layer_config()
590 	return 0;  in mtk_disp_ovl_bind()
615 	irq = platform_get_irq(pdev, 0);  in mtk_disp_ovl_probe()
616 	if (irq < 0)  in mtk_disp_ovl_probe()
624 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in mtk_disp_ovl_probe()
630 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);  in mtk_disp_ovl_probe()
640 	if (ret < 0)  in mtk_disp_ovl_probe()
651 	return 0;  in mtk_disp_ovl_probe()