Lines Matching refs:val
70 u32 val;
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG);
78 if (val)
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val);
80 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED)
82 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) {
86 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED)
88 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR)
91 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);
93 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG);
94 if (val)
95 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val);
96 if (val & DSI_CMD_MODE_STS_ERR_NO_TE)
99 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS)
102 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN)
104 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN)
106 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD)
108 writel(val, d->regs + DSI_CMD_MODE_STS_CLR);
110 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG);
111 if (val)
112 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val);
113 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);
115 val = readl(d->regs + DSI_TG_STS_FLAG);
116 if (val)
117 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val);
118 writel(val, d->regs + DSI_TG_STS_CLR);
120 val = readl(d->regs + DSI_VID_MODE_STS_FLAG);
121 if (val)
122 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val);
123 if (val & DSI_VID_MODE_STS_VSG_RUNNING)
125 if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA)
127 if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC)
129 if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC)
131 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH)
133 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT)
135 if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE |
139 if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH)
141 if (val & DSI_VID_MODE_STS_VSG_RECOVERY)
143 writel(val, d->regs + DSI_VID_MODE_STS_CLR);
219 u32 val;
254 val = readl(d->regs + DSI_DIRECT_CMD_STS);
255 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) {
260 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) {
261 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT;
263 val);
302 u32 val;
324 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ;
326 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE;
334 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT;
335 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
336 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
337 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
338 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT;
339 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
343 val = 0;
345 val |= tx[i] << (i * 8);
347 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
349 val = 0;
351 val |= tx[i + 4] << (i * 8);
352 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
355 val = 0;
357 val |= tx[i + 8] << (i * 8);
358 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
361 val = 0;
363 val |= tx[i + 12] << (i * 8);
364 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
393 u32 val;
398 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ;
399 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT;
400 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT;
401 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN;
402 val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM <<
404 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
410 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL);
411 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN;
412 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN;
413 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);
419 val = readl(d->regs + DSI_CMD_MODE_STS_CTL);
420 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN;
421 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN;
422 writel(val, d->regs + DSI_CMD_MODE_STS_CTL);
439 u32 val;
441 val = 0;
443 val |= DSI_VID_MAIN_CTL_BURST_MODE;
445 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE;
446 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL;
451 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 <<
453 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS;
456 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 <<
458 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS;
461 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18
463 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE;
466 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 <<
468 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS;
485 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0;
490 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0;
492 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT;
494 writel(val, d->regs + DSI_VID_MAIN_CTL);
497 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT;
499 val |= (mode->vsync_start - mode->vdisplay)
502 val |= (mode->vsync_end - mode->vsync_start)
505 val |= (mode->vtotal - mode->vsync_end)
507 writel(val, d->regs + DSI_VID_VSIZE);
562 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT;
564 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT;
566 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT;
567 writel(val, d->regs + DSI_VID_HSIZE1);
570 val = mode->hdisplay * cpp;
571 writel(val, d->regs + DSI_VID_HSIZE2);
572 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val);
626 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT;
627 writel(val, d->regs + DSI_VID_BLKSIZE2);
636 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT;
637 val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK;
638 writel(val, d->regs + DSI_VID_BLKSIZE1);
657 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT;
664 val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT;
665 writel(val, d->regs + DSI_VID_DPHY_TIME);
696 val = readl(d->regs + DSI_VID_BLKSIZE1);
697 val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK;
698 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT;
699 writel(val, d->regs + DSI_VID_BLKSIZE1);
701 val = blkeol_pck <<
703 val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK;
704 writel(val, d->regs + DSI_VID_VCA_SETTING2);
726 val = readl(d->regs + DSI_VID_PCK_TIME);
727 val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK;
728 val |= blkeol_duration <<
730 writel(val, d->regs + DSI_VID_PCK_TIME);
733 val = readl(d->regs + DSI_VID_VCA_SETTING1);
734 val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK;
735 val |= (blkeol_pck - 6) <<
737 writel(val, d->regs + DSI_VID_VCA_SETTING1);
741 val = readl(d->regs + DSI_VID_VCA_SETTING2);
742 val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK;
743 val |= (blkline_pck - 6) <<
745 writel(val, d->regs + DSI_VID_VCA_SETTING2);
752 u32 val;
759 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN |
764 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN;
765 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
768 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT;
769 writel(val, d->regs + DSI_CMD_MODE_CTL);
778 val = 4000 / hs_freq;
779 dev_dbg(d->dev, "UI value: %d\n", val);
780 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT;
781 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK;
782 writel(val, d->regs + DSI_MCTL_DPHY_STATIC);
790 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT;
792 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN;
794 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS;
795 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN |
798 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);
800 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) |
802 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);
808 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) |
811 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);
813 val = DSI_MCTL_MAIN_EN_PLL_START |
818 val |= DSI_MCTL_MAIN_EN_DAT2_EN;
819 writel(val, d->regs + DSI_MCTL_MAIN_EN);
823 val = DSI_MCTL_MAIN_STS_PLL_LOCK |
827 val |= DSI_MCTL_MAIN_STS_DAT2_READY;
828 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) {
840 val = readl(d->regs + DSI_CMD_MODE_CTL);
846 val |= DSI_CMD_MODE_CTL_IF1_LP_EN;
847 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
848 writel(val, d->regs + DSI_CMD_MODE_CTL);
863 u32 val;
923 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
924 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE;
925 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
928 val = readl(d->regs + DSI_CMD_MODE_CTL);
929 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN;
930 writel(val, d->regs + DSI_CMD_MODE_CTL);
933 val = readl(d->regs + DSI_VID_MODE_STS_CTL);
934 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC;
935 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA;
936 writel(val, d->regs + DSI_VID_MODE_STS_CTL);
939 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
940 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN;
941 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
944 val = readl(d->regs + DSI_CMD_MODE_CTL);
950 val |= DSI_CMD_MODE_CTL_IF1_LP_EN;
951 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK;
952 writel(val, d->regs + DSI_CMD_MODE_CTL);
979 u32 val;
987 val = DSI_CMD_MODE_STS_CSM_RUNNING;
988 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) {
1001 u32 val;
1006 val = DSI_VID_MODE_STS_VSG_RUNNING;
1007 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) {
1025 u32 val;
1029 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
1030 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN;
1031 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);