Lines Matching +full:channel +full:- +full:9

1 /* SPDX-License-Identifier: GPL-2.0 */
26 /* Channel interrupts */
32 /* X = 0..9 */
43 /* External sources 0..9 */
72 #define MCDE_EXTSRCXCONF_BPP_XRGB8888 9
81 /* External sources 0..9 */
132 #define MCDE_OVLXCR_BURSTSIZE_HW_2W 9
151 #define MCDE_OVLXCR_ROTBURSTSIZE_HW_2W 9
179 #define MCDE_OVLXCONF2_OPQ BIT(9)
218 /* DPI/TV configuration registers, channel A and B */
230 #define MCDE_TVCR_CKINV BIT(9)
232 /* TV blanking control register 1, channel A and B */
238 /* Pixel processing TV start line, channel A and B */
253  * 0 = 1 pixel HBP, 255 = 256 pixels, so actual value - 1
265 /* TV blanking control register 1, channel A and B */
297 #define MCDE_CRC_SIZE1 BIT(9)
337 /* Channel config 0..3 */
348 /* Channel status 0..3 */
359 /* Sync settings for channel 0..3 */
376 /* Software sync triggers for channel 0..3 */
403 /* Pixel processing control registers for channel A B,  */
467 #define MCDE_CRX1_OUTBPP_24BPP 9
514 /* Channel A+B control registers */