Lines Matching +full:0 +full:x10b0
14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
38 #define LIMA_L2_CACHE_STATUS 0x0008
39 #define LIMA_L2_CACHE_STATUS_COMMAND_BUSY BIT(0)
41 #define LIMA_L2_CACHE_COMMAND 0x0010
42 #define LIMA_L2_CACHE_COMMAND_CLEAR_ALL BIT(0)
43 #define LIMA_L2_CACHE_CLEAR_PAGE 0x0014
44 #define LIMA_L2_CACHE_MAX_READS 0x0018
45 #define LIMA_L2_CACHE_ENABLE 0x001C
46 #define LIMA_L2_CACHE_ENABLE_ACCESS BIT(0)
48 #define LIMA_L2_CACHE_PERFCNT_SRC0 0x0020
49 #define LIMA_L2_CACHE_PERFCNT_VAL0 0x0024
50 #define LIMA_L2_CACHE_PERFCNT_SRC1 0x0028
51 #define LIMA_L2_CACHE_ERFCNT_VAL1 0x002C
54 #define LIMA_GP_VSCL_START_ADDR 0x00
55 #define LIMA_GP_VSCL_END_ADDR 0x04
56 #define LIMA_GP_PLBUCL_START_ADDR 0x08
57 #define LIMA_GP_PLBUCL_END_ADDR 0x0c
58 #define LIMA_GP_PLBU_ALLOC_START_ADDR 0x10
59 #define LIMA_GP_PLBU_ALLOC_END_ADDR 0x14
60 #define LIMA_GP_CMD 0x20
61 #define LIMA_GP_CMD_START_VS BIT(0)
68 #define LIMA_GP_INT_RAWSTAT 0x24
69 #define LIMA_GP_INT_CLEAR 0x28
70 #define LIMA_GP_INT_MASK 0x2C
71 #define LIMA_GP_INT_STAT 0x30
72 #define LIMA_GP_IRQ_VS_END_CMD_LST BIT(0)
91 #define LIMA_GP_WRITE_BOUND_LOW 0x34
92 #define LIMA_GP_PERF_CNT_0_ENABLE 0x3C
93 #define LIMA_GP_PERF_CNT_1_ENABLE 0x40
94 #define LIMA_GP_PERF_CNT_0_SRC 0x44
95 #define LIMA_GP_PERF_CNT_1_SRC 0x48
96 #define LIMA_GP_PERF_CNT_0_VALUE 0x4C
97 #define LIMA_GP_PERF_CNT_1_VALUE 0x50
98 #define LIMA_GP_PERF_CNT_0_LIMIT 0x54
99 #define LIMA_GP_STATUS 0x68
105 #define LIMA_GP_VERSION 0x6C
106 #define LIMA_GP_VSCL_START_ADDR_READ 0x80
107 #define LIMA_GP_PLBCL_START_ADDR_READ 0x84
108 #define LIMA_GP_CONTR_AXI_BUS_ERROR_STAT 0x94
152 #define LIMA_PP_FRAME 0x0000
153 #define LIMA_PP_RSW 0x0004
154 #define LIMA_PP_STACK 0x0030
155 #define LIMA_PP_STACK_SIZE 0x0034
156 #define LIMA_PP_ORIGIN_OFFSET_X 0x0040
157 #define LIMA_PP_WB(i) (0x0100 * (i + 1))
158 #define LIMA_PP_WB_SOURCE_SELECT 0x0000
159 #define LIMA_PP_WB_SOURCE_ADDR 0x0004
161 #define LIMA_PP_VERSION 0x1000
162 #define LIMA_PP_CURRENT_REND_LIST_ADDR 0x1004
163 #define LIMA_PP_STATUS 0x1008
164 #define LIMA_PP_STATUS_RENDERING_ACTIVE BIT(0)
166 #define LIMA_PP_CTRL 0x100c
167 #define LIMA_PP_CTRL_STOP_BUS BIT(0)
172 #define LIMA_PP_INT_RAWSTAT 0x1020
173 #define LIMA_PP_INT_CLEAR 0x1024
174 #define LIMA_PP_INT_MASK 0x1028
175 #define LIMA_PP_INT_STATUS 0x102c
176 #define LIMA_PP_IRQ_END_OF_FRAME BIT(0)
189 #define LIMA_PP_WRITE_BOUNDARY_LOW 0x1044
190 #define LIMA_PP_BUS_ERROR_STATUS 0x1050
191 #define LIMA_PP_PERF_CNT_0_ENABLE 0x1080
192 #define LIMA_PP_PERF_CNT_0_SRC 0x1084
193 #define LIMA_PP_PERF_CNT_0_LIMIT 0x1088
194 #define LIMA_PP_PERF_CNT_0_VALUE 0x108c
195 #define LIMA_PP_PERF_CNT_1_ENABLE 0x10a0
196 #define LIMA_PP_PERF_CNT_1_SRC 0x10a4
197 #define LIMA_PP_PERF_CNT_1_LIMIT 0x10a8
198 #define LIMA_PP_PERF_CNT_1_VALUE 0x10ac
199 #define LIMA_PP_PERFMON_CONTR 0x10b0
200 #define LIMA_PP_PERFMON_BASE 0x10b4
233 #define LIMA_MMU_DTE_ADDR 0x0000
234 #define LIMA_MMU_STATUS 0x0004
235 #define LIMA_MMU_STATUS_PAGING_ENABLED BIT(0)
241 #define LIMA_MMU_STATUS_BUS_ID(x) ((x >> 6) & 0x1F)
243 #define LIMA_MMU_COMMAND 0x0008
244 #define LIMA_MMU_COMMAND_ENABLE_PAGING 0x00
245 #define LIMA_MMU_COMMAND_DISABLE_PAGING 0x01
246 #define LIMA_MMU_COMMAND_ENABLE_STALL 0x02
247 #define LIMA_MMU_COMMAND_DISABLE_STALL 0x03
248 #define LIMA_MMU_COMMAND_ZAP_CACHE 0x04
249 #define LIMA_MMU_COMMAND_PAGE_FAULT_DONE 0x05
250 #define LIMA_MMU_COMMAND_HARD_RESET 0x06
251 #define LIMA_MMU_PAGE_FAULT_ADDR 0x000C
252 #define LIMA_MMU_ZAP_ONE_LINE 0x0010
253 #define LIMA_MMU_INT_RAWSTAT 0x0014
254 #define LIMA_MMU_INT_CLEAR 0x0018
255 #define LIMA_MMU_INT_MASK 0x001C
256 #define LIMA_MMU_INT_PAGE_FAULT BIT(0)
258 #define LIMA_MMU_INT_STATUS 0x0020
260 #define LIMA_VM_FLAG_PRESENT BIT(0)
269 #define LIMA_VM_FLAG_MASK 0x1FF
287 #define LIMA_DLBU_MASTER_TLLIST_PHYS_ADDR 0x0000
288 #define LIMA_DLBU_MASTER_TLLIST_VADDR 0x0004
289 #define LIMA_DLBU_TLLIST_VBASEADDR 0x0008
290 #define LIMA_DLBU_FB_DIM 0x000C
291 #define LIMA_DLBU_TLLIST_CONF 0x0010
292 #define LIMA_DLBU_START_TILE_POS 0x0014
293 #define LIMA_DLBU_PP_ENABLE_MASK 0x0018
296 #define LIMA_BCAST_BROADCAST_MASK 0x0
297 #define LIMA_BCAST_INTERRUPT_MASK 0x4