Lines Matching +full:hard +full:- +full:wires
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
188 * [0-7] @ 0x2000 gen2,gen3
189 * [8-15] @ 0x3000 945,g33,pnv
191 * [0-15] @ 0x3000 gen4,gen5
193 * [0-15] @ 0x100000 gen6,vlv,chv
194 * [0-31] @ 0x100000 gen7+
199 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
207 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
236 #define PRB0_BASE (0x2030 - 0x30)
237 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
238 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
239 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
240 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
241 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
242 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
307 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
308 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
456 /* Enables non-sequential data reads through arbiter
465 /* Arbiter time slice for non-isoch streams */
499 * These defines should cover us well from SNB->HSW with minor exceptions
538 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
625 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
626 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
627 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
628 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
629 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
630 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
631 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
632 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
633 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
634 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
635 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
636 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
642 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
643 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
765 #define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
927 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
1030 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
1047 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
1048 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
1097 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
1171 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
1174 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
1200 /* These are the 4 32-bit write offset registers for each stream