Lines Matching +full:0 +full:x1d0000
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
132 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
137 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
140 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
150 #define DEBUG_RESET_I830 _MMIO(0x6070)
158 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
164 #define IOSF_SB_BUSY (1 << 0)
165 #define IOSF_PORT_BUNIT 0x03
166 #define IOSF_PORT_PUNIT 0x04
167 #define IOSF_PORT_NC 0x11
168 #define IOSF_PORT_DPIO 0x12
169 #define IOSF_PORT_GPIO_NC 0x13
170 #define IOSF_PORT_CCK 0x14
171 #define IOSF_PORT_DPIO_2 0x1a
172 #define IOSF_PORT_FLISDSI 0x1b
173 #define IOSF_PORT_GPIO_SC 0x48
174 #define IOSF_PORT_GPIO_SUS 0xa8
175 #define IOSF_PORT_CCU 0xa9
176 #define CHV_IOSF_PORT_GPIO_N 0x13
177 #define CHV_IOSF_PORT_GPIO_SE 0x48
178 #define CHV_IOSF_PORT_GPIO_E 0xa8
179 #define CHV_IOSF_PORT_GPIO_SW 0xb2
180 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
181 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
184 #define DPIO_DEVFN 0
188 * [0-7] @ 0x2000 gen2,gen3
189 * [8-15] @ 0x3000 945,g33,pnv
191 * [0-15] @ 0x3000 gen4,gen5
193 * [0-15] @ 0x100000 gen6,vlv,chv
194 * [0-31] @ 0x100000 gen7+
196 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
197 #define I830_FENCE_START_MASK 0x07f80000
201 #define I830_FENCE_REG_VALID (1 << 0)
206 #define I915_FENCE_START_MASK 0x0ff00000
209 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
210 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
213 #define I965_FENCE_REG_VALID (1 << 0)
214 #define I965_FENCE_MAX_PITCH_VAL 0x0400
216 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
217 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
219 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
223 #define TILECTL _MMIO(0x101000)
224 #define TILECTL_SWZCTL (1 << 0)
232 #define PGTBL_CTL _MMIO(0x02020)
233 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
234 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
235 #define PGTBL_ER _MMIO(0x02024)
236 #define PRB0_BASE (0x2030 - 0x30)
237 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
238 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
239 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
240 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
241 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
242 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
243 #define RENDER_RING_BASE 0x02000
244 #define BSD_RING_BASE 0x04000
245 #define GEN6_BSD_RING_BASE 0x12000
246 #define GEN8_BSD2_RING_BASE 0x1c000
247 #define GEN11_BSD_RING_BASE 0x1c0000
248 #define GEN11_BSD2_RING_BASE 0x1c4000
249 #define GEN11_BSD3_RING_BASE 0x1d0000
250 #define GEN11_BSD4_RING_BASE 0x1d4000
251 #define XEHP_BSD5_RING_BASE 0x1e0000
252 #define XEHP_BSD6_RING_BASE 0x1e4000
253 #define XEHP_BSD7_RING_BASE 0x1f0000
254 #define XEHP_BSD8_RING_BASE 0x1f4000
255 #define VEBOX_RING_BASE 0x1a000
256 #define GEN11_VEBOX_RING_BASE 0x1c8000
257 #define GEN11_VEBOX2_RING_BASE 0x1d8000
258 #define XEHP_VEBOX3_RING_BASE 0x1e8000
259 #define XEHP_VEBOX4_RING_BASE 0x1f8000
260 #define MTL_GSC_RING_BASE 0x11a000
261 #define GEN12_COMPUTE0_RING_BASE 0x1a000
262 #define GEN12_COMPUTE1_RING_BASE 0x1c000
263 #define GEN12_COMPUTE2_RING_BASE 0x1e000
264 #define GEN12_COMPUTE3_RING_BASE 0x26000
265 #define BLT_RING_BASE 0x22000
266 #define XEHPC_BCS1_RING_BASE 0x3e0000
267 #define XEHPC_BCS2_RING_BASE 0x3e2000
268 #define XEHPC_BCS3_RING_BASE 0x3e4000
269 #define XEHPC_BCS4_RING_BASE 0x3e6000
270 #define XEHPC_BCS5_RING_BASE 0x3e8000
271 #define XEHPC_BCS6_RING_BASE 0x3ea000
272 #define XEHPC_BCS7_RING_BASE 0x3ec000
273 #define XEHPC_BCS8_RING_BASE 0x3ee000
274 #define DG1_GSC_HECI1_BASE 0x00258000
275 #define DG1_GSC_HECI2_BASE 0x00259000
276 #define DG2_GSC_HECI1_BASE 0x00373000
277 #define DG2_GSC_HECI2_BASE 0x00374000
278 #define MTL_GSC_HECI1_BASE 0x00116000
279 #define MTL_GSC_HECI2_BASE 0x00117000
281 #define HECI_H_CSR(base) _MMIO((base) + 0x4)
282 #define HECI_H_CSR_IE REG_BIT(0)
288 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
289 #define HECI_H_GS1_ER_PREP REG_BIT(0)
295 #define HECI_FWSTS1 0xc40
296 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
297 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0
300 #define HECI_FWSTS2 0xc48
301 #define HECI_FWSTS3 0xc60
302 #define HECI_FWSTS4 0xc64
303 #define HECI_FWSTS5 0xc68
305 #define HECI_FWSTS6 0xc6c
307 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
316 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
317 #define GTT_CACHE_EN_ALL 0xF0007FFF
318 #define GEN7_WR_WATERMARK _MMIO(0x4028)
319 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
320 #define ARB_MODE _MMIO(0x4030)
323 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
324 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
326 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
328 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
329 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
331 #define GEN7_ERR_INT _MMIO(0x44040)
351 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
354 #define FPGA_DBG _MMIO(0x42300)
357 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
360 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
362 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
363 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
364 #define SCPD0 _MMIO(0x209c) /* 915+ only */
367 #define GEN2_IER _MMIO(0x20a0)
368 #define GEN2_IIR _MMIO(0x20a4)
369 #define GEN2_IMR _MMIO(0x20a8)
370 #define GEN2_ISR _MMIO(0x20ac)
376 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
379 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
380 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
381 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
382 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
383 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
384 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
385 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
388 #define EIR _MMIO(0x20b0)
389 #define EMR _MMIO(0x20b4)
390 #define ESR _MMIO(0x20b8)
396 #define I915_ERROR_INSTRUCTION (1 << 0)
400 #define INSTPM _MMIO(0x20c0)
408 #define MEM_MODE _MMIO(0x20cc)
412 #define FW_BLC _MMIO(0x20d8)
413 #define FW_BLC2 _MMIO(0x20dc)
414 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
418 #define MM_BURST_LENGTH 0x00700000
419 #define MM_FIFO_WATERMARK 0x0001F000
420 #define LM_BURST_LENGTH 0x00000700
421 #define LM_FIFO_WATERMARK 0x0000001F
422 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
440 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
467 #define MI_ARB_TIME_SLICE_1 (0 << 5)
477 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
484 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
485 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
487 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
489 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
515 #define GT_RENDER_USER_INTERRUPT (1 << 0)
522 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
560 #define I915_ASLE_INTERRUPT (1 << 0)
563 #define GEN6_BSD_RNCID _MMIO(0x12198)
565 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
566 #define GEN7_FF_SCHED_MASK 0x0077070
569 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
570 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
571 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
572 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
574 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
575 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
576 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
577 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
578 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
579 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
580 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
581 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
583 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
588 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
593 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
598 #define DPLL_TEST _MMIO(0x606c)
599 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
608 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
610 #define D_STATE _MMIO(0x6104)
614 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
616 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
653 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
654 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
656 #define RENCLK_GATE_D1 _MMIO(0x6204)
672 # define SV_CLOCK_GATE_DISABLE (1 << 0)
689 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
718 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
720 #define RENCLK_GATE_D2 _MMIO(0x6208)
725 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
728 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
729 #define DEUC _MMIO(0x6214) /* CRL only */
731 #define BXT_RP_STATE_CAP _MMIO(0x138170)
732 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
734 #define MTL_RP_STATE_CAP _MMIO(0x138000)
735 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
736 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
739 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
740 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
741 #define MTL_RPE_MASK REG_GENMASK(8, 0)
743 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
744 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
745 #define PROCHOT_MASK REG_BIT(0)
754 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
756 #define CHV_CLK_CTL1 _MMIO(0x101100)
757 #define VLV_CLK_CTL2 _MMIO(0x101104)
763 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
769 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
773 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
794 #define PCH_3DCGDIS0 _MMIO(0x46020)
798 #define PCH_3DCGDIS1 _MMIO(0x46024)
802 #define RM_TIMEOUT _MMIO(0x42060)
803 #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
804 #define MMIO_TIMEOUT_US(us) ((us) << 0)
836 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
839 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
842 #define DEISR _MMIO(0x44000)
843 #define DEIMR _MMIO(0x44004)
844 #define DEIIR _MMIO(0x44008)
845 #define DEIER _MMIO(0x4400c)
851 #define GTISR _MMIO(0x44010)
852 #define GTIMR _MMIO(0x44014)
853 #define GTIIR _MMIO(0x44018)
854 #define GTIER _MMIO(0x4401c)
860 #define GEN8_MASTER_IRQ _MMIO(0x44200)
876 #define GEN8_GT_RCS_IRQ (1 << 0)
878 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
879 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
880 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
881 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
887 #define GEN8_RCS_IRQ_SHIFT 0
889 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
891 #define GEN8_VECS_IRQ_SHIFT 0
894 #define GEN8_PCU_ISR _MMIO(0x444e0)
895 #define GEN8_PCU_IMR _MMIO(0x444e4)
896 #define GEN8_PCU_IIR _MMIO(0x444e8)
897 #define GEN8_PCU_IER _MMIO(0x444ec)
903 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
904 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
905 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
906 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
913 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
920 #define GEN11_GT_DW0_IRQ (1 << 0)
922 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
926 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
932 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
939 #define IVB_CHICKEN3 _MMIO(0x4200c)
943 #define CHICKEN_PAR1_1 _MMIO(0x42080)
953 #define CHICKEN_PAR2_1 _MMIO(0x42090)
956 #define _CHICKEN_PIPESL_1_A 0x420b0
957 #define _CHICKEN_PIPESL_1_B 0x420b4
960 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
965 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
972 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
973 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
977 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
979 #define DISP_ARB_CTL _MMIO(0x45000)
984 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
1000 #define GMD_ID_DISPLAY _MMIO(0x510a0)
1003 #define GMD_ID_STEP REG_GENMASK(5, 0)
1007 #define SDEISR _MMIO(0xc4000)
1008 #define SDEIMR _MMIO(0xc4004)
1009 #define SDEIIR _MMIO(0xc4008)
1010 #define SDEIER _MMIO(0xc400c)
1018 #define _TRANSA_CHICKEN1 0xf0060
1019 #define _TRANSB_CHICKEN1 0xf1060
1024 #define _TRANSA_CHICKEN2 0xf0064
1025 #define _TRANSB_CHICKEN2 0xf1064
1030 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
1034 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
1050 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
1054 #define SPT_PWM_GRANULARITY (1 << 0)
1055 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
1059 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
1061 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
1070 #define VLV_PMWGICZ _MMIO(0x1300a4)
1072 #define HSW_EDRAM_CAP _MMIO(0x120010)
1073 #define EDRAM_ENABLED 0x1
1074 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
1075 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
1076 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
1078 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
1082 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
1083 #define GEN6_PCODE_ERROR_MASK 0xFF
1084 #define GEN6_PCODE_SUCCESS 0x0
1085 #define GEN6_PCODE_ILLEGAL_CMD 0x1
1086 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
1087 #define GEN6_PCODE_TIMEOUT 0x3
1088 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
1089 #define GEN7_PCODE_TIMEOUT 0x2
1090 #define GEN7_PCODE_ILLEGAL_DATA 0x3
1091 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
1092 #define GEN11_PCODE_LOCKED 0x6
1093 #define GEN11_PCODE_REJECTED 0x11
1094 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
1095 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
1096 #define GEN6_PCODE_READ_RC6VIDS 0x5
1099 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
1100 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
1104 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
1105 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
1106 #define SKL_PCODE_CDCLK_CONTROL 0x7
1107 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
1108 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
1109 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
1110 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
1111 #define GEN6_READ_OC_PARAMS 0xc
1112 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
1113 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
1114 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
1115 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
1116 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
1117 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
1130 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
1131 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
1132 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
1136 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
1139 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
1143 #define GEN6_PCODE_READ_D_COMP 0x10
1144 #define GEN6_PCODE_WRITE_D_COMP 0x11
1145 #define ICL_PCODE_EXIT_TCCOLD 0x12
1146 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
1147 #define DISPLAY_IPS_CONTROL 0x19
1148 #define TGL_PCODE_TCCOLD 0x26
1149 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
1150 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
1151 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
1154 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
1155 #define GEN9_PCODE_SAGV_CONTROL 0x21
1156 #define GEN9_SAGV_DISABLE 0x0
1157 #define GEN9_SAGV_IS_DISABLED 0x1
1158 #define GEN9_SAGV_ENABLE 0x3
1159 #define DG1_PCODE_STATUS 0x7E
1160 #define DG1_UNCORE_GET_INIT_STATUS 0x0
1161 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
1162 #define PCODE_POWER_SETUP 0x7C
1163 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
1164 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
1167 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
1168 #define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
1169 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
1170 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
1172 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
1173 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
1176 #define PCODE_MBOX_DOMAIN_NONE 0x0
1177 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
1178 #define GEN6_PCODE_DATA _MMIO(0x138128)
1181 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
1183 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
1184 #define STOLEN_ACCESS_ALLOWED 0x1
1187 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
1188 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
1204 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
1206 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
1207 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
1208 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
1210 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
1212 #define GGC _MMIO(0x108040)
1216 #define GEN6_GSMBASE _MMIO(0x108100)
1217 #define GEN6_DSMBASE _MMIO(0x1080C0)
1221 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
1226 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
1227 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
1228 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
1229 #define SPI_STATIC_REGIONS _MMIO(0x102090)
1230 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
1231 #define OROM_OFFSET _MMIO(0x1020c0)
1234 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
1237 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
1239 #define MTL_MEDIA_GSI_BASE 0x380000