Lines Matching refs:raw_reg_write
394 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); in ilk_irq_handler()
403 raw_reg_write(regs, SDEIER, 0); in ilk_irq_handler()
410 raw_reg_write(regs, GTIIR, gt_iir); in ilk_irq_handler()
420 raw_reg_write(regs, DEIIR, de_iir); in ilk_irq_handler()
431 raw_reg_write(regs, GEN6_PMIIR, pm_iir); in ilk_irq_handler()
437 raw_reg_write(regs, DEIER, de_ier); in ilk_irq_handler()
439 raw_reg_write(regs, SDEIER, sde_ier); in ilk_irq_handler()
451 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); in gen8_master_intr_disable()
464 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in gen8_master_intr_enable()
501 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); in gen11_master_intr_disable()
514 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); in gen11_master_intr_enable()
557 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); in dg1_master_intr_disable()
564 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); in dg1_master_intr_disable()
571 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_master_intr_enable()
594 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); in dg1_irq_handler()