Lines Matching defs:dev_priv
157 struct drm_i915_private *dev_priv =
158 container_of(work, typeof(*dev_priv), l3_parity.error_work);
159 struct intel_gt *gt = to_gt(dev_priv);
169 mutex_lock(&dev_priv->drm.struct_mutex);
172 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
175 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
177 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
179 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
183 if (drm_WARN_ON_ONCE(&dev_priv->drm,
184 slice >= NUM_L3_SLICES(dev_priv)))
187 dev_priv->l3_parity.which_slice &= ~(1<<slice);
191 error_status = intel_uncore_read(&dev_priv->uncore, reg);
196 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
197 intel_uncore_posting_read(&dev_priv->uncore, reg);
206 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
209 drm_dbg(&dev_priv->drm,
219 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
222 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
224 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
227 mutex_unlock(&dev_priv->drm.struct_mutex);
232 struct drm_i915_private *dev_priv = arg;
233 struct intel_display *display = &dev_priv->display;
236 if (!intel_irqs_enabled(dev_priv))
240 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
249 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
250 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
251 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
271 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
272 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);
275 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
277 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
298 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
300 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
301 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
304 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir);
306 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
317 pmu_irq_stats(dev_priv, ret);
319 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
326 struct drm_i915_private *dev_priv = arg;
327 struct intel_display *display = &dev_priv->display;
330 if (!intel_irqs_enabled(dev_priv))
334 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
343 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
344 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
364 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
365 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);
367 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
389 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
391 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
392 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
403 pmu_irq_stats(dev_priv, ret);
405 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
509 struct drm_i915_private *dev_priv = arg;
510 struct intel_display *display = &dev_priv->display;
511 void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore);
514 if (!intel_irqs_enabled(dev_priv))
524 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
528 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
530 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
535 pmu_irq_stats(dev_priv, IRQ_HANDLED);
661 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
663 struct intel_display *display = &dev_priv->display;
664 struct intel_uncore *uncore = &dev_priv->uncore;
667 dev_priv->irq_mask = ~0u;
669 if (GRAPHICS_VER(dev_priv) == 7)
672 if (IS_HASWELL(dev_priv)) {
677 gen5_gt_irq_reset(to_gt(dev_priv));
682 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
684 struct intel_display *display = &dev_priv->display;
686 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
687 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
689 gen5_gt_irq_reset(to_gt(dev_priv));
694 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
696 struct intel_display *display = &dev_priv->display;
697 struct intel_uncore *uncore = &dev_priv->uncore;
701 gen8_gt_irq_reset(to_gt(dev_priv));
706 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
708 struct intel_display *display = &dev_priv->display;
709 struct intel_gt *gt = to_gt(dev_priv);
712 gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
721 static void dg1_irq_reset(struct drm_i915_private *dev_priv)
723 struct intel_display *display = &dev_priv->display;
724 struct intel_uncore *uncore = &dev_priv->uncore;
728 dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
730 for_each_gt(gt, dev_priv, i)
741 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
743 struct intel_display *display = &dev_priv->display;
744 struct intel_uncore *uncore = &dev_priv->uncore;
747 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
749 gen8_gt_irq_reset(to_gt(dev_priv));
756 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
758 struct intel_display *display = &dev_priv->display;
760 gen5_gt_irq_postinstall(to_gt(dev_priv));
765 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
767 struct intel_display *display = &dev_priv->display;
769 gen5_gt_irq_postinstall(to_gt(dev_priv));
773 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
774 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
777 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
779 struct intel_display *display = &dev_priv->display;
781 gen8_gt_irq_postinstall(to_gt(dev_priv));
784 gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
787 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
789 struct intel_display *display = &dev_priv->display;
790 struct intel_gt *gt = to_gt(dev_priv);
800 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
803 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
805 struct intel_display *display = &dev_priv->display;
806 struct intel_uncore *uncore = &dev_priv->uncore;
811 for_each_gt(gt, dev_priv, i)
822 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
824 struct intel_display *display = &dev_priv->display;
826 gen8_gt_irq_postinstall(to_gt(dev_priv));
830 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
831 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
855 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
860 *eir = intel_uncore_read(&dev_priv->uncore, EIR);
861 intel_uncore_write(&dev_priv->uncore, EIR, *eir);
863 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
877 emr = intel_uncore_read(&dev_priv->uncore, EMR);
878 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
879 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
882 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
885 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir);
888 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
891 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
892 intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
895 static void i915_irq_reset(struct drm_i915_private *dev_priv)
897 struct intel_display *display = &dev_priv->display;
898 struct intel_uncore *uncore = &dev_priv->uncore;
904 dev_priv->irq_mask = ~0u;
907 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
909 struct intel_display *display = &dev_priv->display;
910 struct intel_uncore *uncore = &dev_priv->uncore;
913 gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv));
915 dev_priv->irq_mask =
926 if (DISPLAY_VER(dev_priv) >= 3) {
927 dev_priv->irq_mask &= ~I915_ASLE_INTERRUPT;
931 if (HAS_HOTPLUG(dev_priv)) {
932 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
936 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
943 struct drm_i915_private *dev_priv = arg;
944 struct intel_display *display = &dev_priv->display;
947 if (!intel_irqs_enabled(dev_priv))
951 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
959 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
965 if (HAS_HOTPLUG(dev_priv) &&
974 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
976 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
979 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
982 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
990 pmu_irq_stats(dev_priv, ret);
992 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
997 static void i965_irq_reset(struct drm_i915_private *dev_priv)
999 struct intel_display *display = &dev_priv->display;
1000 struct intel_uncore *uncore = &dev_priv->uncore;
1006 dev_priv->irq_mask = ~0u;
1028 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
1030 struct intel_display *display = &dev_priv->display;
1031 struct intel_uncore *uncore = &dev_priv->uncore;
1034 gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv));
1036 dev_priv->irq_mask =
1051 if (IS_G4X(dev_priv))
1054 gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1061 struct drm_i915_private *dev_priv = arg;
1062 struct intel_display *display = &dev_priv->display;
1065 if (!intel_irqs_enabled(dev_priv))
1069 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1077 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1091 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
1093 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1096 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
1100 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
1104 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
1112 pmu_irq_stats(dev_priv, IRQ_HANDLED);
1114 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1121 * @dev_priv: i915 device instance
1126 void intel_irq_init(struct drm_i915_private *dev_priv)
1130 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
1132 dev_priv->l3_parity.remap_info[i] = NULL;
1135 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)
1136 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16;
1153 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
1155 if (HAS_GMCH(dev_priv)) {
1156 if (IS_CHERRYVIEW(dev_priv))
1158 else if (IS_VALLEYVIEW(dev_priv))
1160 else if (GRAPHICS_VER(dev_priv) == 4)
1165 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
1167 else if (GRAPHICS_VER(dev_priv) >= 11)
1169 else if (GRAPHICS_VER(dev_priv) >= 8)
1176 static void intel_irq_reset(struct drm_i915_private *dev_priv)
1178 if (HAS_GMCH(dev_priv)) {
1179 if (IS_CHERRYVIEW(dev_priv))
1180 cherryview_irq_reset(dev_priv);
1181 else if (IS_VALLEYVIEW(dev_priv))
1182 valleyview_irq_reset(dev_priv);
1183 else if (GRAPHICS_VER(dev_priv) == 4)
1184 i965_irq_reset(dev_priv);
1186 i915_irq_reset(dev_priv);
1188 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
1189 dg1_irq_reset(dev_priv);
1190 else if (GRAPHICS_VER(dev_priv) >= 11)
1191 gen11_irq_reset(dev_priv);
1192 else if (GRAPHICS_VER(dev_priv) >= 8)
1193 gen8_irq_reset(dev_priv);
1195 ilk_irq_reset(dev_priv);
1199 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
1201 if (HAS_GMCH(dev_priv)) {
1202 if (IS_CHERRYVIEW(dev_priv))
1203 cherryview_irq_postinstall(dev_priv);
1204 else if (IS_VALLEYVIEW(dev_priv))
1205 valleyview_irq_postinstall(dev_priv);
1206 else if (GRAPHICS_VER(dev_priv) == 4)
1207 i965_irq_postinstall(dev_priv);
1209 i915_irq_postinstall(dev_priv);
1211 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
1212 dg1_irq_postinstall(dev_priv);
1213 else if (GRAPHICS_VER(dev_priv) >= 11)
1214 gen11_irq_postinstall(dev_priv);
1215 else if (GRAPHICS_VER(dev_priv) >= 8)
1216 gen8_irq_postinstall(dev_priv);
1218 ilk_irq_postinstall(dev_priv);
1224 * @dev_priv: i915 device instance
1233 int intel_irq_install(struct drm_i915_private *dev_priv)
1235 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
1243 dev_priv->irqs_enabled = true;
1245 intel_irq_reset(dev_priv);
1247 ret = request_irq(irq, intel_irq_handler(dev_priv),
1248 IRQF_SHARED, DRIVER_NAME, dev_priv);
1250 dev_priv->irqs_enabled = false;
1254 intel_irq_postinstall(dev_priv);
1261 * @dev_priv: i915 device instance
1266 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
1268 struct intel_display *display = &dev_priv->display;
1269 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
1271 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->irqs_enabled))
1274 intel_irq_reset(dev_priv);
1276 free_irq(irq, dev_priv);
1279 dev_priv->irqs_enabled = false;
1308 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1310 return dev_priv->irqs_enabled;