Lines Matching refs:i915
69 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
183 /* i915 device parameters */
258 * scheduling within i915, which used to be scheduled on the
350 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
352 return i915->gt[0];
355 #define INTEL_INFO(i915) ((i915)->__info)
356 #define RUNTIME_INFO(i915) (&(i915)->__runtime)
357 #define DRIVER_CAPS(i915) (&(i915)->caps)
359 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
363 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
364 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
365 RUNTIME_INFO(i915)->graphics.ip.rel)
366 #define IS_GRAPHICS_VER(i915, from, until) \
367 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
369 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
370 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
371 RUNTIME_INFO(i915)->media.ip.rel)
372 #define IS_MEDIA_VER(i915, from, until) \
373 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
375 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
421 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
423 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
433 IS_SUBPLATFORM(const struct drm_i915_private *i915,
436 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
450 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
451 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
453 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
454 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
455 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
456 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
457 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
458 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
459 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
460 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
461 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
462 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
463 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
464 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
465 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
466 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
467 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
468 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
469 #define IS_IRONLAKE_M(i915) \
470 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
471 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
472 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
473 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
474 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
475 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
476 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
477 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
478 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
479 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
480 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
481 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
482 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
483 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
484 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
485 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
486 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
487 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
488 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
489 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
490 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
491 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
492 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
494 * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE,
495 * so we need to define these even on platforms that the i915 base driver
498 * for i915.
500 #define IS_LUNARLAKE(i915) (0 && i915)
501 #define IS_BATTLEMAGE(i915) (0 && i915)
502 #define IS_PANTHERLAKE(i915) (0 && i915)
504 #define IS_ARROWLAKE_H(i915) \
505 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)
506 #define IS_ARROWLAKE_U(i915) \
507 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)
508 #define IS_ARROWLAKE_S(i915) \
509 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)
510 #define IS_DG2_G10(i915) \
511 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
512 #define IS_DG2_G11(i915) \
513 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
514 #define IS_DG2_G12(i915) \
515 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
516 #define IS_DG2_D(i915) \
517 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_D)
518 #define IS_RAPTORLAKE_S(i915) \
519 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
520 #define IS_ALDERLAKE_P_N(i915) \
521 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
522 #define IS_RAPTORLAKE_P(i915) \
523 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
524 #define IS_RAPTORLAKE_U(i915) \
525 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
526 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
527 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
528 #define IS_BROADWELL_ULT(i915) \
529 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
530 #define IS_BROADWELL_ULX(i915) \
531 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
532 #define IS_HASWELL_ULT(i915) \
533 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
535 #define IS_HASWELL_ULX(i915) \
536 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
537 #define IS_SKYLAKE_ULT(i915) \
538 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
539 #define IS_SKYLAKE_ULX(i915) \
540 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
541 #define IS_KABYLAKE_ULT(i915) \
542 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
543 #define IS_KABYLAKE_ULX(i915) \
544 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
545 #define IS_COFFEELAKE_ULT(i915) \
546 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
547 #define IS_COFFEELAKE_ULX(i915) \
548 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
549 #define IS_COMETLAKE_ULT(i915) \
550 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
551 #define IS_COMETLAKE_ULX(i915) \
552 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
554 #define IS_ICL_WITH_PORT_F(i915) \
555 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
557 #define IS_TIGERLAKE_UY(i915) \
558 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
560 #define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915))
561 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915))
563 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
569 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
571 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
572 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
573 #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
574 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
575 #define HAS_WT(i915) HAS_EDRAM(i915)
577 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
579 #define HAS_LOGICAL_RING_CONTEXTS(i915) \
580 (INTEL_INFO(i915)->has_logical_ring_contexts)
581 #define HAS_LOGICAL_RING_ELSQ(i915) \
582 (INTEL_INFO(i915)->has_logical_ring_elsq)
584 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
586 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
587 #define HAS_PPGTT(i915) \
588 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
589 #define HAS_FULL_PPGTT(i915) \
590 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
592 #define HAS_PAGE_SIZES(i915, sizes) ({ \
594 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
597 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
598 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
601 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \
602 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4))
607 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
608 !(IS_I915G(i915) || IS_I915GM(i915)))
610 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
611 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
612 #define HAS_RC6pp(i915) (false) /* HW was never validated */
614 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
616 #define HAS_PXP(i915) \
617 (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp)
619 #define HAS_HECI_PXP(i915) \
620 (INTEL_INFO(i915)->has_heci_pxp)
622 #define HAS_HECI_GSCFI(i915) \
623 (INTEL_INFO(i915)->has_heci_gscfi)
625 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
627 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
628 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
630 #define HAS_OA_BPC_REPORTING(i915) \
631 (INTEL_INFO(i915)->has_oa_bpc_reporting)
632 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
633 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
634 #define HAS_OAM(i915) \
635 (INTEL_INFO(i915)->has_oam)
641 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
643 #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))
644 #define HAS_LMEM(i915) HAS_REGION(i915, INTEL_REGION_LMEM_0)
646 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
652 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
654 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
656 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
658 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
660 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
662 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
665 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
666 #define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \
667 2 : HAS_L3_DPF(i915))
669 #define HAS_GUC_DEPRIVILEGE(i915) \
670 (INTEL_INFO(i915)->has_guc_deprivilege)
672 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
674 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
676 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
678 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
679 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))