Lines Matching +full:sub +full:- +full:engines
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
12 * distribute, sub license, and/or sell copies of the Software, and to
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
208 * Chaining user engines happens in multiple stages, starting with a
209 * simple lock-less linked list created by intel_engine_add_user(),
215 * in question runs before or after intel_engines_driver_register() --
250 * wq - Driver workqueue for GEM.
259 * unordered_wq - internal workqueue for unordered work
374 return i915->gt[0]; in to_gt()
381 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
383 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
385 #define INTEL_INFO(i915) ((i915)->__info)
386 #define RUNTIME_INFO(i915) (&(i915)->__runtime)
387 #define DRIVER_CAPS(i915) (&(i915)->caps)
389 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
393 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
394 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
395 RUNTIME_INFO(i915)->graphics.ip.rel)
399 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
400 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
401 RUNTIME_INFO(i915)->media.ip.rel)
405 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
407 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
408 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
411 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
415 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
423 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; in __platform_mask_index()
427 pbits * ARRAY_SIZE(info->platform_mask)); in __platform_mask_index()
437 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; in __platform_mask_bit()
447 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; in intel_subplatform()
459 return info->platform_mask[pi] & BIT(pb); in IS_PLATFORM()
469 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; in IS_SUBPLATFORM()
470 const u32 mask = info->platform_mask[pi]; in IS_SUBPLATFORM()
477 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); in IS_SUBPLATFORM()
480 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
481 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
594 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
599 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
603 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
616 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
624 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
625 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
626 #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
630 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
633 (INTEL_INFO(i915)->has_logical_ring_contexts)
635 (INTEL_INFO(i915)->has_logical_ring_elsq)
639 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
647 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
655 (IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4))
657 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
663 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
664 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
667 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
670 (IS_ENABLED(CONFIG_DRM_I915_PXP) && INTEL_INFO(i915)->has_pxp)
673 (INTEL_INFO(i915)->has_heci_pxp)
676 (INTEL_INFO(i915)->has_heci_gscfi)
680 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
681 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
684 (INTEL_INFO(i915)->has_oa_bpc_reporting)
686 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
688 (INTEL_INFO(i915)->has_oam)
694 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
696 #define HAS_REGION(i915, id) (INTEL_INFO(i915)->memory_regions & BIT(id))
699 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
705 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
707 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
709 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
711 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
713 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
715 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
718 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
719 #define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \
723 (INTEL_INFO(i915)->has_guc_deprivilege)
725 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
727 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
729 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)