Lines Matching +full:x +full:- +full:mask
86 * implemented via a per-engine length decoding vfunc.
91 * in the per-engine command tables.
107 * a length mask if not set
129 u32 mask; member
134 * not include a length field) or has a length field mask. The flag
136 * a length mask. All command entries in a command table must include
141 u32 mask; member
149 * A non-zero step value implies that the command may access multiple
155 u32 mask; member
164 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
167 * If the check specifies a non-zero condition_mask then the parser
169 * are non-zero.
173 u32 mask; member
192 #define STD_MI_OPCODE_SHIFT (32 - 9)
193 #define STD_3D_OPCODE_SHIFT (32 - 16)
194 #define STD_2D_OPCODE_SHIFT (32 - 10)
195 #define STD_MFX_OPCODE_SHIFT (32 - 16)
217 /* Command Mask Fixed Len Action
218 ---------------------------------------------------------- */
229 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
231 .reg = { .offset = 1, .mask = 0x007FFFFC },
234 .mask = MI_GLOBAL_GTT,
238 .reg = { .offset = 1, .mask = 0x007FFFFC },
241 .mask = MI_GLOBAL_GTT,
264 .mask = MI_GLOBAL_GTT,
271 .mask = MI_GLOBAL_GTT,
277 .mask = MI_REPORT_PERF_COUNT_GGTT,
283 .mask = MI_GLOBAL_GTT,
291 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
300 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
305 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
322 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
342 .mask = MI_GLOBAL_GTT,
349 .mask = MI_FLUSH_DW_NOTIFY,
354 .mask = MI_FLUSH_DW_USE_GTT,
361 .mask = MI_FLUSH_DW_STORE_INDEX,
369 .mask = MI_GLOBAL_GTT,
374 * It has a length field but it uses a non-standard length bias.
386 .mask = MI_GLOBAL_GTT,
393 .mask = MI_FLUSH_DW_NOTIFY,
398 .mask = MI_FLUSH_DW_USE_GTT,
405 .mask = MI_FLUSH_DW_STORE_INDEX,
413 .mask = MI_GLOBAL_GTT,
423 .mask = MI_GLOBAL_GTT,
430 .mask = MI_FLUSH_DW_NOTIFY,
435 .mask = MI_FLUSH_DW_USE_GTT,
442 .mask = MI_FLUSH_DW_STORE_INDEX,
458 * need to re-enforce the register access checks. We therefore only need to
463 * 2) Those that do not have the default 8-bit length
465 * Note that the default MI length mask chosen for this table is 0xFF, not
467 * cmds on Gen9 use a standard 8-bit Length field.
468 * All the Gen9 blitter instructions are standard 0xFF length mask, and
469 * none allow access to non-general registers, so in fact no BLT cmds are
486 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
489 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
492 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
494 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
500 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
505 .mask = MI_BB_START_OPERAND_MASK,
567 * mask is non-zero the argument of immediate register writes will be
568 * AND-ed with mask, and the command will be rejected if the result
571 * Registers with non-zero mask are only allowed to be written using
576 u32 mask; member
580 /* Convenience macro for adding 32-bit registers. */
588 * Convenience macro for adding 64-bit registers.
591 * access commands only allow 32-bit accesses. Hence, we have to include
592 * entries for both halves of the 64-bit registers.
668 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
671 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
751 DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); in gen7_render_get_cmd_length_mask()
774 DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); in gen7_bsd_get_cmd_length_mask()
787 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); in gen7_blt_get_cmd_length_mask()
798 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); in gen9_blt_get_cmd_length_mask()
817 for (j = 0; j < table->count; j++) { in validate_cmds_sorted()
819 &table->table[j]; in validate_cmds_sorted()
820 u32 curr = desc->cmd.value & desc->cmd.mask; in validate_cmds_sorted()
823 drm_err(&engine->i915->drm, in validate_cmds_sorted()
825 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", in validate_cmds_sorted()
826 engine->name, engine->id, in validate_cmds_sorted()
850 drm_err(&engine->i915->drm, in check_sorted()
852 "entry=%d reg=0x%08X prev=0x%08X\n", in check_sorted()
853 engine->name, engine->id, in check_sorted()
869 for (i = 0; i < engine->reg_table_count; i++) { in validate_regs_sorted()
870 table = &engine->reg_tables[i]; in validate_regs_sorted()
871 if (!check_sorted(engine, table->regs, table->num_regs)) in validate_regs_sorted()
887 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
888 * we mask a command from a batch it could hash to the wrong bucket due to
889 * non-opcode bits being set. But if we don't include those bits, some 3D
893 static inline u32 cmd_header_key(u32 x) in cmd_header_key() argument
895 switch (x >> INSTR_CLIENT_SHIFT) { in cmd_header_key()
898 return x >> STD_MI_OPCODE_SHIFT; in cmd_header_key()
900 return x >> STD_3D_OPCODE_SHIFT; in cmd_header_key()
902 return x >> STD_2D_OPCODE_SHIFT; in cmd_header_key()
912 hash_init(engine->cmd_hash); in init_hash_table()
917 for (j = 0; j < table->count; j++) { in init_hash_table()
919 &table->table[j]; in init_hash_table()
924 return -ENOMEM; in init_hash_table()
926 desc_node->desc = desc; in init_hash_table()
927 hash_add(engine->cmd_hash, &desc_node->node, in init_hash_table()
928 cmd_header_key(desc->cmd.value)); in init_hash_table()
941 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { in fini_hash_table()
942 hash_del(&desc_node->node); in fini_hash_table()
948 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
961 if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 && in intel_engine_init_cmd_parser()
962 engine->class == COPY_ENGINE_CLASS)) in intel_engine_init_cmd_parser()
965 switch (engine->class) { in intel_engine_init_cmd_parser()
967 if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
976 if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
977 engine->reg_tables = hsw_render_reg_tables; in intel_engine_init_cmd_parser()
978 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); in intel_engine_init_cmd_parser()
980 engine->reg_tables = ivb_render_reg_tables; in intel_engine_init_cmd_parser()
981 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); in intel_engine_init_cmd_parser()
983 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; in intel_engine_init_cmd_parser()
988 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; in intel_engine_init_cmd_parser()
991 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; in intel_engine_init_cmd_parser()
992 if (GRAPHICS_VER(engine->i915) == 9) { in intel_engine_init_cmd_parser()
995 engine->get_cmd_length_mask = in intel_engine_init_cmd_parser()
999 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER; in intel_engine_init_cmd_parser()
1000 } else if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1008 if (GRAPHICS_VER(engine->i915) == 9) { in intel_engine_init_cmd_parser()
1009 engine->reg_tables = gen9_blt_reg_tables; in intel_engine_init_cmd_parser()
1010 engine->reg_table_count = in intel_engine_init_cmd_parser()
1012 } else if (IS_HASWELL(engine->i915)) { in intel_engine_init_cmd_parser()
1013 engine->reg_tables = hsw_blt_reg_tables; in intel_engine_init_cmd_parser()
1014 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); in intel_engine_init_cmd_parser()
1016 engine->reg_tables = ivb_blt_reg_tables; in intel_engine_init_cmd_parser()
1017 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); in intel_engine_init_cmd_parser()
1024 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; in intel_engine_init_cmd_parser()
1027 MISSING_CASE(engine->class); in intel_engine_init_cmd_parser()
1032 drm_err(&engine->i915->drm, in intel_engine_init_cmd_parser()
1034 engine->name); in intel_engine_init_cmd_parser()
1038 drm_err(&engine->i915->drm, in intel_engine_init_cmd_parser()
1039 "%s: registers are not sorted\n", engine->name); in intel_engine_init_cmd_parser()
1045 drm_err(&engine->i915->drm, in intel_engine_init_cmd_parser()
1046 "%s: initialised failed!\n", engine->name); in intel_engine_init_cmd_parser()
1051 engine->flags |= I915_ENGINE_USING_CMD_PARSER; in intel_engine_init_cmd_parser()
1056 return -EINVAL; in intel_engine_init_cmd_parser()
1062 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1082 hash_for_each_possible(engine->cmd_hash, desc_node, node, in find_cmd_in_table()
1084 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; in find_cmd_in_table()
1085 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) in find_cmd_in_table()
1106 u32 mask; in find_cmd() local
1108 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) in find_cmd()
1115 mask = engine->get_cmd_length_mask(cmd_header); in find_cmd()
1116 if (!mask) in find_cmd()
1119 default_desc->cmd.value = cmd_header; in find_cmd()
1120 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; in find_cmd()
1121 default_desc->length.mask = mask; in find_cmd()
1122 default_desc->flags = CMD_DESC_SKIP; in find_cmd()
1131 int mid = start + (end - start) / 2; in __find_reg()
1132 int ret = addr - i915_mmio_reg_offset(table[mid].addr); in __find_reg()
1146 const struct drm_i915_reg_table *table = engine->reg_tables; in find_reg()
1148 int count = engine->reg_table_count; in find_reg()
1150 for (; !reg && (count > 0); ++table, --count) in find_reg()
1151 reg = __find_reg(table->regs, table->num_regs, addr); in find_reg()
1182 src = ERR_PTR(-ENODEV); in copy_batch()
1193 unsigned long x, n, remain; in copy_batch() local
1198 * if we only every write full cache-lines. Since we know that in copy_batch()
1210 x = offset_in_page(offset); in copy_batch()
1212 int len = min(remain, PAGE_SIZE - x); in copy_batch()
1216 drm_clflush_virt_range(src + x, len); in copy_batch()
1217 memcpy(ptr, src + x, len); in copy_batch()
1221 remain -= len; in copy_batch()
1222 x = 0; in copy_batch()
1228 memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32)); in copy_batch()
1239 return desc->cmd.value == (cmd & desc->cmd.mask); in cmd_desc_is()
1246 if (desc->flags & CMD_DESC_SKIP) in check_cmd()
1249 if (desc->flags & CMD_DESC_REJECT) { in check_cmd()
1250 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd); in check_cmd()
1254 if (desc->flags & CMD_DESC_REGISTER) { in check_cmd()
1260 const u32 step = desc->reg.step ? desc->reg.step : length; in check_cmd()
1263 for (offset = desc->reg.offset; offset < length; in check_cmd()
1265 const u32 reg_addr = cmd[offset] & desc->reg.mask; in check_cmd()
1270 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n", in check_cmd()
1271 reg_addr, *cmd, engine->name); in check_cmd()
1277 * allowed mask/value pair given in the whitelist entry. in check_cmd()
1279 if (reg->mask) { in check_cmd()
1281 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n", in check_cmd()
1287 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n", in check_cmd()
1294 (cmd[offset + 1] & reg->mask) != reg->value)) { in check_cmd()
1295 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n", in check_cmd()
1303 if (desc->flags & CMD_DESC_BITMASK) { in check_cmd()
1309 if (desc->bits[i].mask == 0) in check_cmd()
1312 if (desc->bits[i].condition_mask != 0) { in check_cmd()
1314 desc->bits[i].condition_offset; in check_cmd()
1316 desc->bits[i].condition_mask; in check_cmd()
1322 if (desc->bits[i].offset >= length) { in check_cmd()
1323 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n", in check_cmd()
1324 *cmd, engine->name); in check_cmd()
1328 dword = cmd[desc->bits[i].offset] & in check_cmd()
1329 desc->bits[i].mask; in check_cmd()
1331 if (dword != desc->bits[i].expected) { in check_cmd()
1332 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n", in check_cmd()
1334 desc->bits[i].mask, in check_cmd()
1335 desc->bits[i].expected, in check_cmd()
1336 dword, engine->name); in check_cmd()
1357 return -EACCES; in check_bbstart()
1363 return -EINVAL; in check_bbstart()
1367 jump_offset = jump_target - batch_addr; in check_bbstart()
1374 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n", in check_bbstart()
1376 return -EINVAL; in check_bbstart()
1395 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n", in check_bbstart()
1397 return -EINVAL; in check_bbstart()
1417 return ERR_PTR(-ENOMEM); in alloc_whitelist()
1425 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations
1436 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1458 batch->size)); in intel_engine_cmd_parser()
1461 cmd = copy_batch(shadow->obj, batch->obj, in intel_engine_cmd_parser()
1491 DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd); in intel_engine_cmd_parser()
1492 ret = -EINVAL; in intel_engine_cmd_parser()
1496 if (desc->flags & CMD_DESC_FIXED) in intel_engine_cmd_parser()
1497 length = desc->length.fixed; in intel_engine_cmd_parser()
1499 length = (*cmd & desc->length.mask) + LENGTH_BIAS; in intel_engine_cmd_parser()
1501 if ((batch_end - cmd) < length) { in intel_engine_cmd_parser()
1502 DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", in intel_engine_cmd_parser()
1505 batch_end - cmd); in intel_engine_cmd_parser()
1506 ret = -EINVAL; in intel_engine_cmd_parser()
1511 ret = -EACCES; in intel_engine_cmd_parser()
1529 ret = -EINVAL; in intel_engine_cmd_parser()
1538 * 1 - starting at offset 0, in privileged mode in intel_engine_cmd_parser()
1539 * 2 - starting at offset batch_len, as non-privileged in intel_engine_cmd_parser()
1544 * entry to chain to the original unsafe non-privileged batch, in intel_engine_cmd_parser()
1551 cmd = page_mask_bits(shadow->obj->mm.mapping); in intel_engine_cmd_parser()
1555 if (ret == -EACCES) { in intel_engine_cmd_parser()
1559 if (IS_HASWELL(engine->i915)) in intel_engine_cmd_parser()
1562 GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7)); in intel_engine_cmd_parser()
1572 i915_gem_object_flush_map(shadow->obj); in intel_engine_cmd_parser()
1576 i915_gem_object_unpin_map(shadow->obj); in intel_engine_cmd_parser()
1581 * i915_cmd_parser_get_version() - get the cmd parser version number
1594 /* If the command parser is not enabled, report 0 - unsupported */ in i915_cmd_parser_get_version()
1620 * for oacontrol state is moving to i915-perf. in i915_cmd_parser_get_version()