Lines Matching +full:0 +full:x29c
27 #define INTEL_GVT_PCI_CLASS_VGA_OTHER 0x80
29 #define INTEL_GVT_PCI_GMCH_CONTROL 0x50
31 #define BDW_GMCH_GMS_MASK 0xff
33 #define INTEL_GVT_PCI_SWSCI 0xe8
37 #define INTEL_GVT_PCI_OPREGION 0xfc
39 #define INTEL_GVT_OPREGION_CLID 0x1AC
40 #define INTEL_GVT_OPREGION_SCIC 0x200
41 #define OPREGION_SCIC_FUNC_MASK 0x1E
43 #define OPREGION_SCIC_SUBFUNC_MASK 0xFF00
45 #define OPREGION_SCIC_EXIT_MASK 0xE0
48 #define INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS 0
50 #define INTEL_GVT_OPREGION_PARM 0x204
54 #define INTEL_GVT_OPREGION_VBT_OFFSET 0x400
62 #define REG50080_FLIP_TYPE_MASK 0x3
63 #define REG50080_FLIP_TYPE_ASYNC 0x1
68 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
69 (_MMIO(0x50090))) : \
70 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
71 (_MMIO(0x50098))) : \
72 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
73 (_MMIO(0x5009C))) : \
74 (_MMIO(0x50080))))); })
78 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
79 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
80 (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
85 (((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \
87 (((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \
91 ((((bit) & 0xffff0000) == 0) && !!((val) & (((bit) << 16))))
98 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
99 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
100 #define FORCEWAKE_GT_GEN9_REG 0xa188
101 #define FORCEWAKE_ACK_GT_GEN9_REG 0x130044
102 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270
103 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
104 #define FORCEWAKE_ACK_HSW_REG 0x130044
114 #define PCH_GPIO_BASE _MMIO(0xc5010)
116 #define PCH_GMBUS0 _MMIO(0xc5100)
117 #define PCH_GMBUS1 _MMIO(0xc5104)
118 #define PCH_GMBUS2 _MMIO(0xc5108)
119 #define PCH_GMBUS3 _MMIO(0xc510c)
120 #define PCH_GMBUS4 _MMIO(0xc5110)
121 #define PCH_GMBUS5 _MMIO(0xc5120)
123 #define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4)
124 #define TRNULLDETCT _MMIO(0x4de8)
125 #define TRINVTILEDETCT _MMIO(0x4dec)
126 #define TRVADR _MMIO(0x4df0)
127 #define TRTTE _MMIO(0x4df4)
128 #define RING_EXCC(base) _MMIO((base) + 0x28)
129 #define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
130 #define VF_GUARDBAND _MMIO(0x83a4)
132 #define BCS_TILE_REGISTER_VAL_OFFSET (0x43*4)
135 #define PCH_PP_STATUS _MMIO(0xc7200)
136 #define PCH_PP_CONTROL _MMIO(0xc7204)
137 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
138 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
139 #define PCH_PP_DIVISOR _MMIO(0xc7210)