211 	struct intel_vgpu_primary_plane_format *plane)  in intel_vgpu_decode_primary_plane()  argument
223 	plane->enabled = !!(val & DISP_ENABLE);  in intel_vgpu_decode_primary_plane()
224 	if (!plane->enabled)  in intel_vgpu_decode_primary_plane()
228 		plane->tiled = val & PLANE_CTL_TILED_MASK;  in intel_vgpu_decode_primary_plane()
240 		plane->bpp = skl_pixel_formats[fmt].bpp;  in intel_vgpu_decode_primary_plane()
241 		plane->drm_format = skl_pixel_formats[fmt].drm_format;  in intel_vgpu_decode_primary_plane()
243 		plane->tiled = val & DISP_TILED;  in intel_vgpu_decode_primary_plane()
245 		plane->bpp = bdw_pixel_formats[fmt].bpp;  in intel_vgpu_decode_primary_plane()
246 		plane->drm_format = bdw_pixel_formats[fmt].drm_format;  in intel_vgpu_decode_primary_plane()
249 	if (!plane->bpp) {  in intel_vgpu_decode_primary_plane()
254 	plane->hw_format = fmt;  in intel_vgpu_decode_primary_plane()
256 	plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_primary_plane()
257 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_primary_plane()
260 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_primary_plane()
261 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {  in intel_vgpu_decode_primary_plane()
263 				plane->base);  in intel_vgpu_decode_primary_plane()
267 	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,  in intel_vgpu_decode_primary_plane()
270 		_PRI_PLANE_STRIDE_MASK, plane->bpp);  in intel_vgpu_decode_primary_plane()
272 	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>  in intel_vgpu_decode_primary_plane()
274 	plane->width += 1;  in intel_vgpu_decode_primary_plane()
275 	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &  in intel_vgpu_decode_primary_plane()
277 	plane->height += 1;	/* raw height is one minus the real value */  in intel_vgpu_decode_primary_plane()
280 	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>  in intel_vgpu_decode_primary_plane()
282 	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>  in intel_vgpu_decode_primary_plane()
342 	struct intel_vgpu_cursor_plane_format *plane)  in intel_vgpu_decode_cursor_plane()  argument
356 	plane->enabled = (mode != MCURSOR_MODE_DISABLE);  in intel_vgpu_decode_cursor_plane()
357 	if (!plane->enabled)  in intel_vgpu_decode_cursor_plane()
366 	plane->mode = mode;  in intel_vgpu_decode_cursor_plane()
367 	plane->bpp = cursor_pixel_formats[index].bpp;  in intel_vgpu_decode_cursor_plane()
368 	plane->drm_format = cursor_pixel_formats[index].drm_format;  in intel_vgpu_decode_cursor_plane()
369 	plane->width = cursor_pixel_formats[index].width;  in intel_vgpu_decode_cursor_plane()
370 	plane->height = cursor_pixel_formats[index].height;  in intel_vgpu_decode_cursor_plane()
380 	plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_cursor_plane()
381 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_cursor_plane()
384 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_cursor_plane()
385 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {  in intel_vgpu_decode_cursor_plane()
387 				plane->base);  in intel_vgpu_decode_cursor_plane()
392 	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;  in intel_vgpu_decode_cursor_plane()
393 	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;  in intel_vgpu_decode_cursor_plane()
394 	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;  in intel_vgpu_decode_cursor_plane()
395 	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;  in intel_vgpu_decode_cursor_plane()
397 	plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));  in intel_vgpu_decode_cursor_plane()
398 	plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));  in intel_vgpu_decode_cursor_plane()
422 	struct intel_vgpu_sprite_plane_format *plane)  in intel_vgpu_decode_sprite_plane()  argument
434 	plane->enabled = !!(val & SPRITE_ENABLE);  in intel_vgpu_decode_sprite_plane()
435 	if (!plane->enabled)  in intel_vgpu_decode_sprite_plane()
438 	plane->tiled = !!(val & SPRITE_TILED);  in intel_vgpu_decode_sprite_plane()
448 	plane->hw_format = fmt;  in intel_vgpu_decode_sprite_plane()
449 	plane->bpp = sprite_pixel_formats[fmt].bpp;  in intel_vgpu_decode_sprite_plane()
482 	plane->drm_format = drm_format;  in intel_vgpu_decode_sprite_plane()
484 	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;  in intel_vgpu_decode_sprite_plane()
485 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))  in intel_vgpu_decode_sprite_plane()
488 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);  in intel_vgpu_decode_sprite_plane()
489 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {  in intel_vgpu_decode_sprite_plane()
491 				plane->base);  in intel_vgpu_decode_sprite_plane()
495 	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &  in intel_vgpu_decode_sprite_plane()
499 	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>  in intel_vgpu_decode_sprite_plane()
501 	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>  in intel_vgpu_decode_sprite_plane()
503 	plane->height += 1;	/* raw height is one minus the real value */  in intel_vgpu_decode_sprite_plane()
504 	plane->width += 1;	/* raw width is one minus the real value */  in intel_vgpu_decode_sprite_plane()
507 	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;  in intel_vgpu_decode_sprite_plane()
508 	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;  in intel_vgpu_decode_sprite_plane()
511 	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>  in intel_vgpu_decode_sprite_plane()
513 	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>  in intel_vgpu_decode_sprite_plane()