Lines Matching full:plane

204  * intel_vgpu_decode_primary_plane - Decode primary plane
206  * @plane: primary plane to save decoded info
207  * This function is called for decoding plane
213 	struct intel_vgpu_primary_plane_format *plane)
225 	plane->enabled = !!(val & DISP_ENABLE);
226 	if (!plane->enabled)
230 		plane->tiled = val & PLANE_CTL_TILED_MASK;
242 		plane->bpp = skl_pixel_formats[fmt].bpp;
243 		plane->drm_format = skl_pixel_formats[fmt].drm_format;
245 		plane->tiled = val & DISP_TILED;
247 		plane->bpp = bdw_pixel_formats[fmt].bpp;
248 		plane->drm_format = bdw_pixel_formats[fmt].drm_format;
251 	if (!plane->bpp) {
256 	plane->hw_format = fmt;
258 	plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;
259 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
262 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
263 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
264 		gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
265 				plane->base);
269 	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
272 		_PRI_PLANE_STRIDE_MASK, plane->bpp);
274 	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>
276 	plane->width += 1;
277 	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &
279 	plane->height += 1;	/* raw height is one minus the real value */
282 	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
284 	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
335  * intel_vgpu_decode_cursor_plane - Decode sprite plane
337  * @plane: cursor plane to save decoded info
338  * This function is called for decoding plane
344 	struct intel_vgpu_cursor_plane_format *plane)
358 	plane->enabled = (mode != MCURSOR_MODE_DISABLE);
359 	if (!plane->enabled)
368 	plane->mode = mode;
369 	plane->bpp = cursor_pixel_formats[index].bpp;
370 	plane->drm_format = cursor_pixel_formats[index].drm_format;
371 	plane->width = cursor_pixel_formats[index].width;
372 	plane->height = cursor_pixel_formats[index].height;
382 	plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;
383 	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
386 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
387 	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
388 		gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
389 				plane->base);
394 	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
395 	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
396 	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
397 	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
399 	plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
400 	plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));