Lines Matching +full:32 +full:- +full:bit
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
56 {DRM_FORMAT_C8, 8, "8-bit Indexed"},
57 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
58 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
59 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
61 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
62 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
64 /* non-supported format has bpp default to 0 */
69 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
70 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
71 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
72 {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
74 {DRM_FORMAT_C8, 8, "8-bit Indexed"},
75 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
76 {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
77 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
79 {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
80 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
81 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
82 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
84 /* non-supported format has bpp default to 0 */
143 return -EINVAL;
156 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
157 struct intel_display *display = &dev_priv->display;
176 else if (bpp == 16 || bpp == 32 || bpp == 64)
202 * intel_vgpu_decode_primary_plane - Decode primary plane
208 * 0 on success, non-zero if failed.
213 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
214 struct intel_display *display = &dev_priv->display;
220 return -ENODEV;
223 plane->enabled = !!(val & DISP_ENABLE);
224 if (!plane->enabled)
225 return -ENODEV;
228 plane->tiled = val & PLANE_CTL_TILED_MASK;
236 gvt_vgpu_err("Out-of-bounds pixel format index\n");
237 return -EINVAL;
240 plane->bpp = skl_pixel_formats[fmt].bpp;
241 plane->drm_format = skl_pixel_formats[fmt].drm_format;
243 plane->tiled = val & DISP_TILED;
245 plane->bpp = bdw_pixel_formats[fmt].bpp;
246 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
249 if (!plane->bpp) {
250 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
251 return -EINVAL;
254 plane->hw_format = fmt;
256 plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;
257 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
258 return -EINVAL;
260 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
261 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
263 plane->base);
264 return -EINVAL;
267 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
270 _PRI_PLANE_STRIDE_MASK, plane->bpp);
272 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>
274 plane->width += 1;
275 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &
277 plane->height += 1; /* raw height is one minus the real value */
280 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
282 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
298 {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
299 {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
300 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
301 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
303 /* non-supported format has bpp default to 0 */
333 * intel_vgpu_decode_cursor_plane - Decode sprite plane
339 * 0 on success, non-zero if failed.
344 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
345 struct intel_display *display = &dev_priv->display;
352 return -ENODEV;
356 plane->enabled = (mode != MCURSOR_MODE_DISABLE);
357 if (!plane->enabled)
358 return -ENODEV;
363 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
364 return -EINVAL;
366 plane->mode = mode;
367 plane->bpp = cursor_pixel_formats[index].bpp;
368 plane->drm_format = cursor_pixel_formats[index].drm_format;
369 plane->width = cursor_pixel_formats[index].width;
370 plane->height = cursor_pixel_formats[index].height;
380 plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;
381 if (!vgpu_gmadr_is_valid(vgpu, plane->base))
382 return -EINVAL;
384 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
385 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
387 plane->base);
388 return -EINVAL;
392 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
393 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
394 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
395 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
397 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
398 plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));