Lines Matching +full:max +full:- +full:rpm

2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
44 struct intel_gvt *gvt = vgpu->gvt;
45 struct intel_gt *gt = gvt->gt;
53 node = &vgpu->gm.high_gm_node;
59 node = &vgpu->gm.low_gm_node;
66 mutex_lock(&gt->ggtt->vm.mutex);
68 ret = i915_gem_gtt_insert(&gt->ggtt->vm, NULL, node,
73 mutex_unlock(&gt->ggtt->vm.mutex);
83 struct intel_gvt *gvt = vgpu->gvt;
84 struct intel_gt *gt = gvt->gt;
95 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
98 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
103 mutex_lock(&gt->ggtt->vm.mutex);
104 drm_mm_remove_node(&vgpu->gm.low_gm_node);
105 mutex_unlock(&gt->ggtt->vm.mutex);
111 struct intel_gvt *gvt = vgpu->gvt;
112 struct intel_gt *gt = gvt->gt;
114 mutex_lock(&gt->ggtt->vm.mutex);
115 drm_mm_remove_node(&vgpu->gm.low_gm_node);
116 drm_mm_remove_node(&vgpu->gm.high_gm_node);
117 mutex_unlock(&gt->ggtt->vm.mutex);
121 * intel_vgpu_write_fence - write fence registers owned by a vGPU
133 struct intel_gvt *gvt = vgpu->gvt;
134 struct drm_i915_private *i915 = gvt->gt->i915;
135 struct intel_uncore *uncore = gvt->gt->uncore;
139 assert_rpm_wakelock_held(uncore->rpm);
141 if (drm_WARN_ON(&i915->drm, fence >= vgpu_fence_sz(vgpu)))
144 reg = vgpu->fence.regs[fence];
145 if (drm_WARN_ON(&i915->drm, !reg))
148 fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
149 fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
169 struct intel_gvt *gvt = vgpu->gvt;
170 struct intel_uncore *uncore = gvt->gt->uncore;
175 if (drm_WARN_ON(&gvt->gt->i915->drm, !vgpu_fence_sz(vgpu)))
178 wakeref = intel_runtime_pm_get(uncore->rpm);
180 mutex_lock(&gvt->gt->ggtt->vm.mutex);
183 reg = vgpu->fence.regs[i];
185 vgpu->fence.regs[i] = NULL;
187 mutex_unlock(&gvt->gt->ggtt->vm.mutex);
189 intel_runtime_pm_put(uncore->rpm, wakeref);
194 struct intel_gvt *gvt = vgpu->gvt;
195 struct intel_uncore *uncore = gvt->gt->uncore;
200 wakeref = intel_runtime_pm_get(uncore->rpm);
203 mutex_lock(&gvt->gt->ggtt->vm.mutex);
206 reg = i915_reserve_fence(gvt->gt->ggtt);
210 vgpu->fence.regs[i] = reg;
215 mutex_unlock(&gvt->gt->ggtt->vm.mutex);
216 intel_runtime_pm_put(uncore->rpm, wakeref);
223 reg = vgpu->fence.regs[i];
227 vgpu->fence.regs[i] = NULL;
229 mutex_unlock(&gvt->gt->ggtt->vm.mutex);
230 intel_runtime_pm_put(uncore->rpm, wakeref);
231 return -ENOSPC;
236 struct intel_gvt *gvt = vgpu->gvt;
238 gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
239 gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
240 gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
246 struct intel_gvt *gvt = vgpu->gvt;
247 unsigned long request, avail, max, taken;
250 if (!conf->low_mm || !conf->high_mm || !conf->fence) {
252 return -EINVAL;
256 max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
257 taken = gvt->gm.vgpu_allocated_low_gm_size;
258 avail = max - taken;
259 request = conf->low_mm;
267 max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
268 taken = gvt->gm.vgpu_allocated_high_gm_size;
269 avail = max - taken;
270 request = conf->high_mm;
278 max = gvt_fence_sz(gvt) - HOST_FENCE;
279 taken = gvt->fence.vgpu_allocated_fence_num;
280 avail = max - taken;
281 request = conf->fence;
288 gvt->gm.vgpu_allocated_low_gm_size += conf->low_mm;
289 gvt->gm.vgpu_allocated_high_gm_size += conf->high_mm;
290 gvt->fence.vgpu_allocated_fence_num += conf->fence;
295 gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n",
297 BYTES_TO_MB(max), BYTES_TO_MB(taken));
298 return -ENOSPC;
302 * intel_vgpu_free_resource() - free HW resource owned by a vGPU
316 * intel_vgpu_reset_resource - reset resource state owned by a vGPU
324 struct intel_gvt *gvt = vgpu->gvt;
327 with_intel_runtime_pm(gvt->gt->uncore->rpm, wakeref)
332 * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU