Lines Matching +full:spin +full:- +full:up
1 // SPDX-License-Identifier: MIT
26 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
37 return -1;
49 return -1;
68 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)
76 obj = i915_gem_object_create_internal(vm->i915, 64 << 10);
80 end = obj->base.size / sizeof(u32) - 1;
113 loop = cs - base;
134 GEM_BUG_ON(cs - base > end);
190 mutex_lock(&rps->lock);
193 mutex_unlock(&rps->lock);
196 GEM_BUG_ON(rps->last_freq != freq);
197 mutex_unlock(&rps->lock);
222 struct intel_rps *rps = >->rps;
226 struct igt_spinner spin;
230 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
233 if (igt_spinner_init(&spin, gt))
234 return -ENOMEM;
237 saved_work = rps->work.func;
238 rps->work.func = dummy_rps_work;
241 intel_rps_disable(>->rps);
255 rq = igt_spinner_create_request(&spin,
256 engine->kernel_context,
266 if (!igt_wait_for_spinner(&spin, rq)) {
268 engine->name);
269 igt_spinner_end(&spin);
271 intel_gt_set_wedged(engine->gt);
272 err = -EIO;
276 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
278 intel_uncore_write_fw(gt->uncore, GEN6_RP_CUR_UP_EI, 0);
281 intel_uncore_write_fw(gt->uncore,
283 intel_uncore_write_fw(gt->uncore,
286 intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL,
289 if (wait_for(intel_uncore_read_fw(gt->uncore,
294 engine->name);
295 err = -ENODEV;
304 cycles_[i] = -intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI);
309 cycles_[i] += intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI);
322 intel_uncore_write_fw(gt->uncore, GEN6_RP_CONTROL, 0);
323 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
325 igt_spinner_end(&spin);
334 engine->name, cycles, time, dt, expected,
335 gt->clock_frequency / 1000);
340 engine->name);
341 err = -EINVAL;
347 engine->name);
348 err = -EINVAL;
352 if (igt_flush_test(gt->i915))
353 err = -EIO;
358 intel_rps_enable(>->rps);
361 igt_spinner_fini(&spin);
364 rps->work.func = saved_work;
366 if (err == -ENODEV) /* skipped, don't report a fail */
375 struct intel_rps *rps = >->rps;
379 struct igt_spinner spin;
393 if (IS_CHERRYVIEW(gt->i915)) /* XXX fragile PCU */
396 if (igt_spinner_init(&spin, gt))
397 return -ENOMEM;
400 saved_work = rps->work.func;
401 rps->work.func = dummy_rps_work;
415 rq = igt_spinner_create_request(&spin,
416 engine->kernel_context,
425 if (!igt_wait_for_spinner(&spin, rq)) {
427 engine->name);
428 igt_spinner_end(&spin);
430 intel_gt_set_wedged(engine->gt);
431 err = -EIO;
435 if (rps_set_check(rps, rps->min_freq) != rps->min_freq) {
437 engine->name, rps->min_freq, read_cagf(rps));
438 igt_spinner_end(&spin);
441 err = -EINVAL;
445 for (f = rps->min_freq + 1; f < rps->max_freq; f++) {
452 if (rps_set_check(rps, rps->min_freq) != rps->min_freq) {
454 engine->name, rps->min_freq, read_cagf(rps));
455 igt_spinner_end(&spin);
458 err = -EINVAL;
467 min = rps_set_check(rps, rps->min_freq);
470 igt_spinner_end(&spin);
474 engine->name,
475 rps->min_freq, intel_gpu_freq(rps, rps->min_freq),
476 rps->max_freq, intel_gpu_freq(rps, rps->max_freq),
480 if (limit != rps->max_freq) {
481 u32 throttle = intel_uncore_read(gt->uncore,
485 engine->name, throttle & GT0_PERF_LIMIT_REASONS_MASK);
489 if (igt_flush_test(gt->i915)) {
490 err = -EIO;
496 igt_spinner_fini(&spin);
499 rps->work.func = saved_work;
514 min_gpu_freq = rps->min_freq;
515 max_gpu_freq = rps->max_freq;
522 wakeref = intel_runtime_pm_get(rps_to_uncore(rps)->rpm);
528 snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
537 intel_runtime_pm_put(rps_to_uncore(rps)->rpm, wakeref);
547 dc = READ_ONCE(*cntr) - dc;
548 dt = ktime_get() - dt;
573 dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0));
576 dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc;
577 dt = ktime_get() - dt;
608 struct intel_rps *rps = >->rps;
623 if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
630 saved_work = rps->work.func;
631 rps->work.func = dummy_rps_work;
645 engine->kernel_context->vm, false,
661 err = rq->engine->emit_bb_start(rq,
668 if (wait_for(intel_uncore_read(engine->uncore, CS_GPR(0)),
671 engine->name);
675 min.freq = rps->min_freq;
678 max.freq = rps->max_freq;
682 engine->name,
694 engine->name,
699 for (f = min.freq + 1; f <= rps->max_freq; f++) {
708 engine->name,
716 err = -EINTR; /* ignore error, continue on with test */
721 i915_gem_object_flush_map(vma->obj);
722 i915_gem_object_unpin_map(vma->obj);
728 if (igt_flush_test(gt->i915))
729 err = -EIO;
735 rps->work.func = saved_work;
747 struct intel_rps *rps = >->rps;
762 if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
769 saved_work = rps->work.func;
770 rps->work.func = dummy_rps_work;
784 engine->kernel_context->vm, true,
800 err = rq->engine->emit_bb_start(rq,
809 engine->name);
813 min.freq = rps->min_freq;
816 max.freq = rps->max_freq;
820 engine->name,
832 engine->name,
837 for (f = min.freq + 1; f <= rps->max_freq; f++) {
846 engine->name,
854 err = -EINTR; /* ignore error, continue on with test */
859 i915_gem_object_flush_map(vma->obj);
860 i915_gem_object_unpin_map(vma->obj);
866 if (igt_flush_test(gt->i915))
867 err = -EIO;
873 rps->work.func = saved_work;
888 GEM_BUG_ON(rps->pm_iir);
897 struct igt_spinner *spin)
899 struct intel_uncore *uncore = engine->uncore;
906 rps_set_check(rps, rps->min_freq);
908 rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
915 if (!igt_wait_for_spinner(spin, rq)) {
917 engine->name);
919 intel_gt_set_wedged(engine->gt);
920 return -EIO;
925 engine->name);
926 igt_spinner_end(spin);
928 return -EINVAL;
931 if (!(rps->pm_events & GEN6_PM_RP_UP_THRESHOLD)) {
932 pr_err("%s: RPS did not register UP interrupt\n",
933 engine->name);
935 return -EINVAL;
938 if (rps->last_freq != rps->min_freq) {
940 engine->name);
942 return -EINVAL;
946 timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout);
952 igt_spinner_end(spin);
955 if (rps->cur_freq != rps->min_freq) {
956 pr_err("%s: Frequency unexpectedly changed [up], now %d!\n",
957 engine->name, intel_rps_read_actual_frequency(rps));
958 return -EINVAL;
961 if (!(rps->pm_iir & GEN6_PM_RP_UP_THRESHOLD)) {
962 pr_err("%s: UP interrupt not recorded for spinner, pm_iir:%x, prev_up:%x, up_threshold:%x, up_ei:%x\n",
963 engine->name, rps->pm_iir,
967 return -EINVAL;
976 struct intel_uncore *uncore = engine->uncore;
979 rps_set_check(rps, rps->max_freq);
981 if (!(rps->pm_events & GEN6_PM_RP_DOWN_THRESHOLD)) {
983 engine->name);
984 return -EINVAL;
987 if (rps->last_freq != rps->max_freq) {
989 engine->name);
990 return -EINVAL;
994 timeout = intel_gt_pm_interval_to_ns(engine->gt, timeout);
999 if (rps->cur_freq != rps->max_freq) {
1001 engine->name,
1003 return -EINVAL;
1006 if (!(rps->pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT))) {
1008 engine->name, rps->pm_iir,
1015 return -EINVAL;
1024 struct intel_rps *rps = >->rps;
1028 struct igt_spinner spin;
1037 if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
1042 pm_events = rps->pm_events;
1045 return -ENODEV;
1048 if (igt_spinner_init(&spin, gt))
1049 return -ENOMEM;
1052 saved_work = rps->work.func;
1053 rps->work.func = dummy_rps_work;
1056 /* Keep the engine busy with a spinner; expect an UP! */
1058 intel_gt_pm_wait_for_idle(engine->gt);
1063 err = __rps_up_interrupt(rps, engine, &spin);
1069 intel_gt_pm_wait_for_idle(engine->gt);
1075 intel_rc6_disable(>->rc6);
1079 intel_rc6_enable(>->rc6);
1087 if (igt_flush_test(gt->i915))
1088 err = -EIO;
1090 igt_spinner_fini(&spin);
1093 rps->work.func = saved_work;
1105 dE = librapl_energy_uJ() - dE;
1106 dt = ktime_get() - dt;
1136 struct intel_rps *rps = >->rps;
1140 struct igt_spinner spin;
1149 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
1152 if (!librapl_supported(gt->i915))
1155 if (igt_spinner_init(&spin, gt))
1156 return -ENOMEM;
1159 saved_work = rps->work.func;
1160 rps->work.func = dummy_rps_work;
1174 rq = igt_spinner_create_request(&spin,
1175 engine->kernel_context,
1185 if (!igt_wait_for_spinner(&spin, rq)) {
1187 engine->name);
1188 igt_spinner_end(&spin);
1190 intel_gt_set_wedged(engine->gt);
1191 err = -EIO;
1195 max.freq = rps->max_freq;
1198 min.freq = rps->min_freq;
1201 igt_spinner_end(&spin);
1205 engine->name,
1218 engine->name);
1219 err = -EINVAL;
1223 if (igt_flush_test(gt->i915)) {
1224 err = -EIO;
1229 igt_spinner_fini(&spin);
1232 rps->work.func = saved_work;
1240 struct intel_rps *rps = >->rps;
1243 struct igt_spinner spin;
1253 if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
1256 if (igt_spinner_init(&spin, gt))
1257 return -ENOMEM;
1276 rps->cur_freq = rps->min_freq;
1279 intel_rc6_disable(>->rc6);
1280 GEM_BUG_ON(rps->last_freq != rps->min_freq);
1282 rq = igt_spinner_create_request(&spin,
1283 engine->kernel_context,
1293 max.freq = wait_for_freq(rps, rps->max_freq, 500);
1296 igt_spinner_end(&spin);
1299 min.freq = wait_for_freq(rps, rps->min_freq, 2000);
1303 engine->name,
1310 engine->name);
1311 err = -EINVAL;
1315 intel_rc6_enable(>->rc6);
1318 if (igt_flush_test(gt->i915))
1319 err = -EIO;
1324 igt_spinner_fini(&spin);