Lines Matching refs:wal
100 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt,
103 wal->gt = gt;
104 wal->name = name;
105 wal->engine_name = engine_name;
110 static void wa_init_finish(struct i915_wa_list *wal)
113 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
114 struct i915_wa *list = kmemdup_array(wal->list, wal->count,
118 kfree(wal->list);
119 wal->list = list;
123 if (!wal->count)
126 gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n",
127 wal->wa_count, wal->name, wal->engine_name);
131 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
137 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
146 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
149 struct drm_i915_private *i915 = wal->gt->i915;
150 unsigned int start = 0, end = wal->count;
156 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
159 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
166 if (wal->list) {
167 memcpy(list, wal->list, sizeof(*wa) * wal->count);
168 kfree(wal->list);
171 wal->list = list;
177 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
179 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
182 wa_ = &wal->list[mid];
193 wal->wa_count++;
201 wal->wa_count++;
202 wa_ = &wal->list[wal->count++];
205 while (wa_-- > wal->list) {
216 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
227 _wa_add(wal, &wa);
230 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
242 _wa_add(wal, &wa);
246 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
248 wa_add(wal, reg, clear, set, clear | set, false);
252 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
254 wa_mcr_add(wal, reg, clear, set, clear | set, false);
258 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
260 wa_write_clr_set(wal, reg, ~0, set);
264 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
266 wa_write_clr_set(wal, reg, set, set);
270 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
272 wa_mcr_write_clr_set(wal, reg, set, set);
276 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
278 wa_write_clr_set(wal, reg, clr, 0);
282 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
284 wa_mcr_write_clr_set(wal, reg, clr, 0);
299 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
301 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
305 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
307 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
311 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
313 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
317 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
319 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
323 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
326 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
330 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
333 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
337 struct i915_wa_list *wal)
339 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
343 struct i915_wa_list *wal)
345 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
349 struct i915_wa_list *wal)
351 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
354 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
357 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
366 wa_masked_en(wal, HDC_CHICKEN0,
378 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
381 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
391 wa_masked_field_set(wal, GEN7_GT_MODE,
397 struct i915_wa_list *wal)
401 gen8_ctx_workarounds_init(engine, wal);
404 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
411 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
414 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
417 wa_masked_en(wal, HDC_CHICKEN0,
425 struct i915_wa_list *wal)
427 gen8_ctx_workarounds_init(engine, wal);
430 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
433 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
437 struct i915_wa_list *wal)
447 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
449 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
455 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
461 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
467 wa_masked_en(wal, CACHE_MODE_1,
472 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
476 wa_masked_en(wal, HDC_CHICKEN0,
494 wa_masked_en(wal, HDC_CHICKEN0,
502 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
506 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
520 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
523 wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
529 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
533 struct i915_wa_list *wal)
563 wa_masked_field_set(wal, GEN7_GT_MODE,
573 struct i915_wa_list *wal)
575 gen9_ctx_workarounds_init(engine, wal);
576 skl_tune_iz_hashing(engine, wal);
580 struct i915_wa_list *wal)
582 gen9_ctx_workarounds_init(engine, wal);
585 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
589 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
594 struct i915_wa_list *wal)
598 gen9_ctx_workarounds_init(engine, wal);
602 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
606 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
611 struct i915_wa_list *wal)
613 gen9_ctx_workarounds_init(engine, wal);
616 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
621 struct i915_wa_list *wal)
623 gen9_ctx_workarounds_init(engine, wal);
626 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
630 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
635 struct i915_wa_list *wal)
638 wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
647 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
650 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
656 wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
661 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
665 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
666 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
671 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
679 struct i915_wa_list *wal)
681 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
682 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
684 wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
689 struct i915_wa_list *wal)
705 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
709 wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
731 wa_add(wal,
739 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
742 wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
747 struct i915_wa_list *wal)
749 gen12_ctx_workarounds_init(engine, wal);
752 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3,
756 wa_masked_en(wal, HIZ_CHICKEN,
761 struct i915_wa_list *wal)
763 dg2_ctx_gt_tuning_init(engine, wal);
766 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
770 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
773 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
776 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
779 wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
783 struct i915_wa_list *wal)
787 dg2_ctx_gt_tuning_init(engine, wal);
796 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
800 struct i915_wa_list *wal)
804 xelpg_ctx_gt_tuning_init(engine, wal);
809 wa_masked_field_set(wal, VF_PREEMPTION,
813 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
817 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
820 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
824 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
827 wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
831 struct i915_wa_list *wal)
858 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
862 struct i915_wa_list *wal)
873 wa_write_clr_set(wal,
888 struct i915_wa_list *wal)
891 fakewa_disable_nestedbb_mode(engine, wal);
893 gen12_ctx_gt_mocs_init(engine, wal);
898 struct i915_wa_list *wal,
903 wa_init_start(wal, engine->gt, name, engine->name);
911 gen12_ctx_gt_fake_wa_init(engine, wal);
917 xelpg_ctx_workarounds_init(engine, wal);
919 dg2_ctx_workarounds_init(engine, wal);
921 dg1_ctx_workarounds_init(engine, wal);
923 gen12_ctx_workarounds_init(engine, wal);
925 icl_ctx_workarounds_init(engine, wal);
927 cfl_ctx_workarounds_init(engine, wal);
929 glk_ctx_workarounds_init(engine, wal);
931 kbl_ctx_workarounds_init(engine, wal);
933 bxt_ctx_workarounds_init(engine, wal);
935 skl_ctx_workarounds_init(engine, wal);
937 chv_ctx_workarounds_init(engine, wal);
939 bdw_ctx_workarounds_init(engine, wal);
941 gen7_ctx_workarounds_init(engine, wal);
943 gen6_ctx_workarounds_init(engine, wal);
950 wa_init_finish(wal);
960 struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
969 if (wal->count == 0)
978 cs = intel_ring_begin(rq, (wal->count * 2 + 6));
980 cs = intel_ring_begin(rq, (wal->count * 2 + 2));
985 fw = wal_get_fw_for_rmw(uncore, wal);
987 intel_gt_mcr_lock(wal->gt, &flags);
991 *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
992 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1000 intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) :
1022 intel_gt_mcr_unlock(wal->gt, flags);
1035 struct i915_wa_list *wal)
1038 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
1042 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1044 gen4_gt_workarounds_init(gt, wal);
1047 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
1051 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1053 g4x_gt_workarounds_init(gt, wal);
1055 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
1059 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1064 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1067 wa_masked_dis(wal,
1072 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
1073 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
1076 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1080 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1083 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1089 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
1093 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1096 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
1098 wa_add(wal,
1104 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
1108 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
1142 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
1146 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1151 gen9_wa_init_mcr(i915, wal);
1155 wa_write_or(wal,
1165 wa_write_or(wal,
1171 wa_write_or(wal,
1177 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1179 gen9_gt_workarounds_init(gt, wal);
1182 wa_write_or(wal,
1188 wa_write_or(wal,
1194 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1196 gen9_gt_workarounds_init(gt, wal);
1200 wa_write_or(wal,
1205 wa_write_or(wal,
1210 wa_write_or(wal,
1216 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1218 gen9_gt_workarounds_init(gt, wal);
1222 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1224 gen9_gt_workarounds_init(gt, wal);
1227 wa_write_or(wal,
1232 wa_write_or(wal,
1237 static void __set_mcr_steering(struct i915_wa_list *wal,
1246 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);
1258 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
1261 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice);
1270 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1297 __add_mcr_wa(gt, wal, 0, subslice);
1301 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1364 __add_mcr_wa(gt, wal, slice, subslice);
1375 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2);
1376 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
1383 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
1387 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1391 icl_wa_init_mcr(gt, wal);
1394 wa_write_clr_set(wal,
1402 wa_write_or(wal,
1410 wa_write_or(wal,
1417 wa_write_or(wal,
1425 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1429 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1433 wa_mcr_write_or(wal,
1441 wa_write_or(wal,
1449 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1459 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal)
1469 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),
1475 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1477 icl_wa_init_mcr(gt, wal);
1480 wa_14011060649(gt, wal);
1483 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1494 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
1499 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1501 gen12_gt_workarounds_init(gt, wal);
1504 wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
1509 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
1513 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1515 xehp_init_mcr(gt, wal);
1518 wa_14011060649(gt, wal);
1522 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1526 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1531 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1537 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
1541 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1542 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1543 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1544 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1547 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
1551 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
1555 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1558 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1559 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1562 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
1567 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1570 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
1581 wa_16021867713(struct intel_gt *gt, struct i915_wa_list *wal)
1588 wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),
1593 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1595 wa_16021867713(gt, wal);
1604 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
1612 wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1615 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
1631 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
1634 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1635 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1639 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1640 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1645 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
1649 gt_tuning_settings(gt, wal);
1653 xelpmp_gt_workarounds_init(gt, wal);
1661 xelpg_gt_workarounds_init(gt, wal);
1663 dg2_gt_workarounds_init(gt, wal);
1665 dg1_gt_workarounds_init(gt, wal);
1667 gen12_gt_workarounds_init(gt, wal);
1669 icl_gt_workarounds_init(gt, wal);
1671 cfl_gt_workarounds_init(gt, wal);
1673 glk_gt_workarounds_init(gt, wal);
1675 kbl_gt_workarounds_init(gt, wal);
1677 gen9_gt_workarounds_init(gt, wal);
1679 skl_gt_workarounds_init(gt, wal);
1681 hsw_gt_workarounds_init(gt, wal);
1683 vlv_gt_workarounds_init(gt, wal);
1685 ivb_gt_workarounds_init(gt, wal);
1687 snb_gt_workarounds_init(gt, wal);
1689 ilk_gt_workarounds_init(gt, wal);
1691 g4x_gt_workarounds_init(gt, wal);
1693 gen4_gt_workarounds_init(gt, wal);
1702 struct i915_wa_list *wal = >->wa_list;
1704 wa_init_start(wal, gt, "GT", "global");
1705 gt_init_workarounds(gt, wal);
1706 wa_init_finish(wal);
1725 static void wa_list_apply(const struct i915_wa_list *wal)
1727 struct intel_gt *gt = wal->gt;
1734 if (!wal->count)
1737 fw = wal_get_fw_for_rmw(uncore, wal);
1743 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1764 wa_verify(gt, wa, val, wal->name, "application");
1779 const struct i915_wa_list *wal,
1789 fw = wal_get_fw_for_rmw(uncore, wal);
1795 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1796 ok &= wa_verify(wal->gt, wa, wa->is_mcr ?
1799 wal->name, from);
1829 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1835 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1842 _wa_add(wal, &wa);
1846 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
1853 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1860 _wa_add(wal, &wa);
1864 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1866 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1870 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
1872 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
2135 const struct i915_wa_list *wal = &engine->whitelist;
2141 if (!wal->count)
2144 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
2164 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2193 wa_masked_field_set(wal,
2201 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2209 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2217 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2224 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2233 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
2240 wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
2253 wa_masked_en(wal,
2261 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
2269 wa_write_or(wal, GEN7_FF_THREAD_MODE,
2273 wa_mcr_masked_en(wal,
2281 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2285 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
2296 wa_masked_en(wal,
2304 wa_masked_en(wal,
2312 wa_write_or(wal,
2320 wa_write_clr_set(wal,
2324 wa_write_clr_set(wal,
2333 wa_mcr_write_or(wal,
2338 wa_write_or(wal,
2343 wa_mcr_write_clr_set(wal,
2349 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
2356 wa_write_or(wal,
2361 wa_masked_en(wal,
2421 wa_masked_en(wal,
2430 wa_write_or(wal,
2437 wa_masked_en(wal,
2444 wa_masked_en(wal,
2449 wa_mcr_write_or(wal,
2455 wa_mcr_write_clr_set(wal,
2462 wa_mcr_write_or(wal,
2467 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
2469 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,
2471 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,
2477 wa_masked_en(wal,
2480 wa_masked_dis(wal,
2488 wa_masked_en(wal,
2498 wa_write_clr_set(wal,
2507 wa_masked_en(wal,
2515 wa_masked_en(wal,
2521 wa_masked_dis(wal,
2532 wa_write_clr_set(wal,
2541 wa_masked_en(wal,
2548 wa_masked_en(wal,
2553 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
2560 wa_masked_en(wal,
2572 wa_masked_field_set(wal,
2586 wa_masked_en(wal,
2596 wa_masked_en(wal,
2601 wa_masked_en(wal,
2605 wa_masked_en(wal,
2625 wa_masked_field_set(wal,
2631 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
2639 wa_masked_dis(wal,
2646 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
2662 wa_add(wal, ECOSKPD(RENDER_RING_BASE),
2669 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2675 wa_write(wal,
2681 wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
2687 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2706 struct i915_wa_list *wal)
2711 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
2719 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
2723 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
2726 static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2740 wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
2747 wa_masked_en(wal, XEHP_CCS_MODE, mode);
2760 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2765 add_render_compute_tuning_settings(gt, wal);
2781 wa_mcr_masked_en(wal,
2790 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
2793 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING);
2802 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2807 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2814 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
2818 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
2825 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
2830 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
2836 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
2839 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);
2847 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
2852 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
2862 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
2870 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2875 engine_fake_wa_init(engine, wal);
2883 general_render_compute_wa_init(engine, wal);
2884 ccs_engine_wa_mode(engine, wal);
2888 ccs_engine_wa_init(engine, wal);
2890 rcs_engine_wa_init(engine, wal);
2892 xcs_engine_wa_init(engine, wal);
2897 struct i915_wa_list *wal = &engine->wa_list;
2899 wa_init_start(wal, engine->gt, "engine", engine->name);
2900 engine_init_workarounds(engine, wal);
2901 wa_init_finish(wal);
2973 const struct i915_wa_list *wal,
2985 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
2994 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3011 const struct i915_wa_list * const wal,
3022 if (!wal->count)
3026 wal->count * sizeof(u32));
3052 err = wa_list_srm(rq, wal, vma);
3074 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3078 if (!wa_verify(wal->gt, wa, results[i], wal->name, from))