Lines Matching +full:rp1 +full:- +full:clocks
1 // SPDX-License-Identifier: MIT
43 return rps_to_gt(rps)->i915; in rps_to_i915()
48 return rps_to_gt(rps)->uncore; in rps_to_uncore()
55 return >_to_guc(gt)->slpc; in rps_to_slpc()
62 return intel_uc_uses_guc_slpc(>->uc); in rps_uses_slpc()
67 return mask & ~rps->pm_intrmsk_mbz; in rps_pm_sanitize_mask()
90 last = engine->stats.rps; in rps_timer()
91 engine->stats.rps = dt; in rps_timer()
99 last = rps->pm_timestamp; in rps_timer()
100 rps->pm_timestamp = timestamp; in rps_timer()
110 * at the lowest clocks required to sustain the heaviest in rps_timer()
115 * video decode on vcs followed by colour post-processing in rps_timer()
116 * on vecs, followed by general post-processing on rcs. in rps_timer()
117 * Since multi-engines being active does imply a single in rps_timer()
133 rps->pm_interval); in rps_timer()
135 if (100 * busy > rps->power.up_threshold * dt && in rps_timer()
136 rps->cur_freq < rps->max_freq_softlimit) { in rps_timer()
137 rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD; in rps_timer()
138 rps->pm_interval = 1; in rps_timer()
139 queue_work(gt->i915->unordered_wq, &rps->work); in rps_timer()
140 } else if (100 * busy < rps->power.down_threshold * dt && in rps_timer()
141 rps->cur_freq > rps->min_freq_softlimit) { in rps_timer()
142 rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD; in rps_timer()
143 rps->pm_interval = 1; in rps_timer()
144 queue_work(gt->i915->unordered_wq, &rps->work); in rps_timer()
146 rps->last_adj = 0; in rps_timer()
149 mod_timer(&rps->timer, in rps_timer()
150 jiffies + msecs_to_jiffies(rps->pm_interval)); in rps_timer()
151 rps->pm_interval = min(rps->pm_interval * 2, BUSY_MAX_EI); in rps_timer()
157 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); in rps_start_timer()
158 rps->pm_interval = 1; in rps_start_timer()
159 mod_timer(&rps->timer, jiffies + 1); in rps_start_timer()
164 timer_delete_sync(&rps->timer); in rps_stop_timer()
165 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); in rps_stop_timer()
166 cancel_work_sync(&rps->work); in rps_stop_timer()
174 if (val > rps->min_freq_softlimit) in rps_pm_mask()
179 if (val < rps->max_freq_softlimit) in rps_pm_mask()
182 mask &= rps->pm_events; in rps_pm_mask()
189 memset(&rps->ei, 0, sizeof(rps->ei)); in rps_reset_ei()
198 GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", in rps_enable_interrupts()
199 rps->pm_events, rps_pm_mask(rps, rps->last_freq)); in rps_enable_interrupts()
203 spin_lock_irq(gt->irq_lock); in rps_enable_interrupts()
204 gen6_gt_pm_enable_irq(gt, rps->pm_events); in rps_enable_interrupts()
205 spin_unlock_irq(gt->irq_lock); in rps_enable_interrupts()
207 intel_uncore_write(gt->uncore, in rps_enable_interrupts()
208 GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq)); in rps_enable_interrupts()
226 spin_lock_irq(gt->irq_lock); in rps_reset_interrupts()
227 if (GRAPHICS_VER(gt->i915) >= 11) in rps_reset_interrupts()
232 rps->pm_iir = 0; in rps_reset_interrupts()
233 spin_unlock_irq(gt->irq_lock); in rps_reset_interrupts()
240 intel_uncore_write(gt->uncore, in rps_disable_interrupts()
243 spin_lock_irq(gt->irq_lock); in rps_disable_interrupts()
245 spin_unlock_irq(gt->irq_lock); in rps_disable_interrupts()
247 intel_synchronize_irq(gt->i915); in rps_disable_interrupts()
255 cancel_work_sync(&rps->work); in rps_disable_interrupts()
283 if (i915->fsb_freq <= 3200000) in gen5_rps_init()
285 else if (i915->fsb_freq <= 4800000) in gen5_rps_init()
292 cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) { in gen5_rps_init()
293 rps->ips.m = cparams[i].m; in gen5_rps_init()
294 rps->ips.c = cparams[i].c; in gen5_rps_init()
306 drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n", in gen5_rps_init()
309 rps->min_freq = fmax; in gen5_rps_init()
310 rps->efficient_freq = fstart; in gen5_rps_init()
311 rps->max_freq = fmin; in gen5_rps_init()
326 * Prevent division-by-zero if we are asking too fast. in __ips_chipset_val()
331 dt = now - ips->last_time1; in __ips_chipset_val()
333 return ips->chipset_power; in __ips_chipset_val()
335 /* FIXME: handle per-counter overflow */ in __ips_chipset_val()
340 delta = total - ips->last_count1; in __ips_chipset_val()
342 result = div_u64(div_u64(ips->m * delta, dt) + ips->c, 10); in __ips_chipset_val()
344 ips->last_count1 = total; in __ips_chipset_val()
345 ips->last_time1 = now; in __ips_chipset_val()
347 ips->chipset_power = result; in __ips_chipset_val()
363 return m * x / 127 - b; in ips_mch_val()
381 if (INTEL_INFO(i915)->is_mobile) in pvid_to_extvid()
382 return max(vd - 1125, 0); in pvid_to_extvid()
397 dt = now - ips->last_time2; in __gen5_ips_update()
405 delta = count - ips->last_count2; in __gen5_ips_update()
407 ips->last_count2 = count; in __gen5_ips_update()
408 ips->last_time2 = now; in __gen5_ips_update()
411 ips->gfx_power = div_u64(delta * 1181, dt * 10); in __gen5_ips_update()
417 __gen5_ips_update(&rps->ips); in gen5_rps_update()
425 val = rps->max_freq - val; in gen5_invert_freq()
426 val = rps->min_freq + val; in gen5_invert_freq()
440 drm_dbg(&rps_to_i915(rps)->drm, in __gen5_rps_set()
442 return -EBUSY; /* still busy with another command */ in __gen5_rps_set()
504 /* Program P-state weights to account for frequency power adjustment */ in init_emon()
553 struct intel_display *display = i915->display; in gen5_rps_enable()
597 drm_err(&uncore->i915->drm, in gen5_rps_enable()
601 __gen5_rps_set(rps, rps->cur_freq); in gen5_rps_enable()
603 rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC); in gen5_rps_enable()
604 rps->ips.last_count1 += intel_uncore_read(uncore, DDREC); in gen5_rps_enable()
605 rps->ips.last_count1 += intel_uncore_read(uncore, CSIEC); in gen5_rps_enable()
606 rps->ips.last_time1 = jiffies_to_msecs(jiffies); in gen5_rps_enable()
608 rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC); in gen5_rps_enable()
609 rps->ips.last_time2 = ktime_get_raw_ns(); in gen5_rps_enable()
615 rps->ips.corr = init_emon(uncore); in gen5_rps_enable()
623 struct intel_display *display = i915->display; in gen5_rps_disable()
638 __gen5_rps_set(rps, rps->idle_freq); in gen5_rps_disable()
660 limits = rps->max_freq_softlimit << 23; in rps_limits()
661 if (val <= rps->min_freq_softlimit) in rps_limits()
662 limits |= rps->min_freq_softlimit << 14; in rps_limits()
664 limits = rps->max_freq_softlimit << 24; in rps_limits()
665 if (val <= rps->min_freq_softlimit) in rps_limits()
666 limits |= rps->min_freq_softlimit << 16; in rps_limits()
675 struct intel_uncore *uncore = gt->uncore; in rps_set_power()
678 lockdep_assert_held(&rps->power.mutex); in rps_set_power()
680 if (new_power == rps->power.mode) in rps_set_power()
704 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
710 rps->power.up_threshold, ei_up, in rps_set_power()
711 rps->power.down_threshold, ei_down); in rps_set_power()
717 ei_up * rps->power.up_threshold * 10)); in rps_set_power()
724 rps->power.down_threshold * 10)); in rps_set_power()
727 (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) | in rps_set_power()
735 rps->power.mode = new_power; in rps_set_power()
742 new_power = rps->power.mode; in gen6_rps_set_thresholds()
743 switch (rps->power.mode) { in gen6_rps_set_thresholds()
745 if (val > rps->efficient_freq + 1 && in gen6_rps_set_thresholds()
746 val > rps->cur_freq) in gen6_rps_set_thresholds()
751 if (val <= rps->efficient_freq && in gen6_rps_set_thresholds()
752 val < rps->cur_freq) in gen6_rps_set_thresholds()
754 else if (val >= rps->rp0_freq && in gen6_rps_set_thresholds()
755 val > rps->cur_freq) in gen6_rps_set_thresholds()
760 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && in gen6_rps_set_thresholds()
761 val < rps->cur_freq) in gen6_rps_set_thresholds()
766 if (val <= rps->min_freq_softlimit) in gen6_rps_set_thresholds()
768 if (val >= rps->max_freq_softlimit) in gen6_rps_set_thresholds()
771 mutex_lock(&rps->power.mutex); in gen6_rps_set_thresholds()
772 if (rps->power.interactive) in gen6_rps_set_thresholds()
775 mutex_unlock(&rps->power.mutex); in gen6_rps_set_thresholds()
783 mutex_lock(&rps->power.mutex); in intel_rps_mark_interactive()
785 if (!rps->power.interactive++ && intel_rps_is_active(rps)) in intel_rps_mark_interactive()
788 GEM_BUG_ON(!rps->power.interactive); in intel_rps_mark_interactive()
789 rps->power.interactive--; in intel_rps_mark_interactive()
791 mutex_unlock(&rps->power.mutex); in intel_rps_mark_interactive()
823 vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in vlv_rps_set()
824 err = vlv_iosf_sb_write(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_REQ, val); in vlv_rps_set()
825 vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in vlv_rps_set()
838 if (val == rps->last_freq) in rps_set()
852 rps->last_freq = val; in rps_set()
862 GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq); in intel_rps_unpark()
868 mutex_lock(&rps->lock); in intel_rps_unpark()
872 clamp(rps->cur_freq, in intel_rps_unpark()
873 rps->min_freq_softlimit, in intel_rps_unpark()
874 rps->max_freq_softlimit)); in intel_rps_unpark()
876 mutex_unlock(&rps->lock); in intel_rps_unpark()
878 rps->pm_iir = 0; in intel_rps_unpark()
903 if (rps->last_freq <= rps->idle_freq) in intel_rps_park()
920 rps_set(rps, rps->idle_freq, false); in intel_rps_park()
933 adj = rps->last_adj; in intel_rps_park()
937 adj = -2; in intel_rps_park()
938 rps->last_adj = adj; in intel_rps_park()
939 rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq); in intel_rps_park()
940 if (rps->cur_freq < rps->efficient_freq) { in intel_rps_park()
941 rps->cur_freq = rps->efficient_freq; in intel_rps_park()
942 rps->last_adj = 0; in intel_rps_park()
945 GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq); in intel_rps_park()
955 return slpc->boost_freq; in intel_rps_get_boost_frequency()
957 return intel_gpu_freq(rps, rps->boost_freq); in intel_rps_get_boost_frequency()
967 if (val < rps->min_freq || val > rps->max_freq) in rps_set_boost_freq()
968 return -EINVAL; in rps_set_boost_freq()
970 mutex_lock(&rps->lock); in rps_set_boost_freq()
971 if (val != rps->boost_freq) { in rps_set_boost_freq()
972 rps->boost_freq = val; in rps_set_boost_freq()
973 boost = atomic_read(&rps->num_waiters); in rps_set_boost_freq()
975 mutex_unlock(&rps->lock); in rps_set_boost_freq()
977 queue_work(rps_to_gt(rps)->i915->unordered_wq, &rps->work); in rps_set_boost_freq()
1003 if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING) in intel_rps_dec_waiters()
1008 atomic_dec(&rps->num_waiters); in intel_rps_dec_waiters()
1020 if (test_bit(CONTEXT_LOW_LATENCY, &rq->context->flags)) in intel_rps_boost()
1024 if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) { in intel_rps_boost()
1025 struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps; in intel_rps_boost()
1031 if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING) in intel_rps_boost()
1035 if (!atomic_fetch_inc(&slpc->num_waiters)) { in intel_rps_boost()
1040 if (slpc->min_freq_softlimit >= slpc->boost_freq) in intel_rps_boost()
1044 rq->fence.context, rq->fence.seqno); in intel_rps_boost()
1045 queue_work(rps_to_gt(rps)->i915->unordered_wq, in intel_rps_boost()
1046 &slpc->boost_work); in intel_rps_boost()
1052 if (atomic_fetch_inc(&rps->num_waiters)) in intel_rps_boost()
1059 rq->fence.context, rq->fence.seqno); in intel_rps_boost()
1061 if (READ_ONCE(rps->cur_freq) < rps->boost_freq) in intel_rps_boost()
1062 queue_work(rps_to_gt(rps)->i915->unordered_wq, &rps->work); in intel_rps_boost()
1064 WRITE_ONCE(rps->boosts, rps->boosts + 1); /* debug only */ in intel_rps_boost()
1072 lockdep_assert_held(&rps->lock); in intel_rps_set()
1073 GEM_BUG_ON(val > rps->max_freq); in intel_rps_set()
1074 GEM_BUG_ON(val < rps->min_freq); in intel_rps_set()
1095 rps->cur_freq = val; in intel_rps_set()
1114 u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ? in mtl_get_freq_caps()
1117 u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ? in mtl_get_freq_caps()
1122 caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap); in mtl_get_freq_caps()
1123 caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap); in mtl_get_freq_caps()
1124 caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe); in mtl_get_freq_caps()
1135 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ in __gen6_rps_get_freq_caps()
1137 caps->rp0_freq = (rp_state_cap >> 16) & 0xff; in __gen6_rps_get_freq_caps()
1138 caps->rp1_freq = (rp_state_cap >> 8) & 0xff; in __gen6_rps_get_freq_caps()
1139 caps->min_freq = (rp_state_cap >> 0) & 0xff; in __gen6_rps_get_freq_caps()
1141 caps->rp0_freq = (rp_state_cap >> 0) & 0xff; in __gen6_rps_get_freq_caps()
1143 caps->rp1_freq = REG_FIELD_GET(RPE_MASK, in __gen6_rps_get_freq_caps()
1144 intel_uncore_read(to_gt(i915)->uncore, in __gen6_rps_get_freq_caps()
1147 caps->rp1_freq = (rp_state_cap >> 8) & 0xff; in __gen6_rps_get_freq_caps()
1148 caps->min_freq = (rp_state_cap >> 16) & 0xff; in __gen6_rps_get_freq_caps()
1157 caps->rp0_freq *= GEN9_FREQ_SCALER; in __gen6_rps_get_freq_caps()
1158 caps->rp1_freq *= GEN9_FREQ_SCALER; in __gen6_rps_get_freq_caps()
1159 caps->min_freq *= GEN9_FREQ_SCALER; in __gen6_rps_get_freq_caps()
1164 * gen6_rps_get_freq_caps - Get freq caps exposed by HW
1187 rps->rp0_freq = caps.rp0_freq; in gen6_rps_init()
1188 rps->rp1_freq = caps.rp1_freq; in gen6_rps_init()
1189 rps->min_freq = caps.min_freq; in gen6_rps_init()
1192 rps->max_freq = rps->rp0_freq; in gen6_rps_init()
1194 rps->efficient_freq = rps->rp1_freq; in gen6_rps_init()
1202 if (snb_pcode_read(rps_to_gt(rps)->uncore, in gen6_rps_init()
1205 rps->efficient_freq = in gen6_rps_init()
1208 rps->min_freq, in gen6_rps_init()
1209 rps->max_freq); in gen6_rps_init()
1218 rps->power.mode = -1; in rps_reset()
1219 rps->last_freq = -1; in rps_reset()
1221 if (rps_set(rps, rps->min_freq, true)) { in rps_reset()
1222 drm_err(&i915->drm, "Failed to reset RPS to initial values\n"); in rps_reset()
1226 rps->cur_freq = rps->min_freq; in rps_reset()
1234 struct intel_uncore *uncore = gt->uncore; in gen9_rps_enable()
1237 if (GRAPHICS_VER(gt->i915) == 9) in gen9_rps_enable()
1239 GEN9_FREQUENCY(rps->rp1_freq)); in gen9_rps_enable()
1243 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; in gen9_rps_enable()
1253 HSW_FREQUENCY(rps->rp1_freq)); in gen8_rps_enable()
1257 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; in gen8_rps_enable()
1270 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | in gen6_rps_enable()
1283 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_max_freq()
1285 switch (gt->info.sseu.eu_total) { in chv_rps_max_freq()
1310 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_GPU_DUTYCYCLE_REG); in chv_rps_rpe_freq()
1321 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_guar_freq()
1331 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, FB_GFX_FMIN_AT_VMIN_FUSE); in chv_rps_min_freq()
1360 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | in chv_rps_enable()
1365 vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in chv_rps_enable()
1368 vlv_iosf_sb_write(&i915->drm, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val); in chv_rps_enable()
1370 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); in chv_rps_enable()
1372 vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in chv_rps_enable()
1375 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, in chv_rps_enable()
1378 drm_dbg(&i915->drm, "GPLL enabled? %s\n", in chv_rps_enable()
1380 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); in chv_rps_enable()
1388 u32 val, rp1; in vlv_rps_guar_freq() local
1390 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE); in vlv_rps_guar_freq()
1392 rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK; in vlv_rps_guar_freq()
1393 rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; in vlv_rps_guar_freq()
1395 return rp1; in vlv_rps_guar_freq()
1403 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE); in vlv_rps_max_freq()
1417 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_LO); in vlv_rps_rpe_freq()
1419 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FMAX_FUSE_HI); in vlv_rps_rpe_freq()
1430 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_LFM) & 0xff; in vlv_rps_min_freq()
1434 * a BYT-M B0 the above register contains 0xbf. Moreover when setting in vlv_rps_min_freq()
1464 rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED; in vlv_rps_enable()
1466 vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in vlv_rps_enable()
1470 vlv_iosf_sb_write(&i915->drm, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val); in vlv_rps_enable()
1472 val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_enable()
1474 vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in vlv_rps_enable()
1477 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, in vlv_rps_enable()
1480 drm_dbg(&i915->drm, "GPLL enabled? %s\n", in vlv_rps_enable()
1482 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); in vlv_rps_enable()
1497 pxvid = intel_uncore_read(uncore, PXVFREQ(rps->cur_freq)); in __ips_gfx_val()
1514 corr = div_u64(corr * 150142 * state1, 10000) - 78642; in __ips_gfx_val()
1515 corr2 = div_u64(corr, 100000) * ips->corr; in __ips_gfx_val()
1522 return ips->gfx_power + state2; in __ips_gfx_val()
1553 if (rps->max_freq <= rps->min_freq) in intel_rps_enable()
1575 rps->min_freq, rps->max_freq, in intel_rps_enable()
1576 intel_gpu_freq(rps, rps->min_freq), in intel_rps_enable()
1577 intel_gpu_freq(rps, rps->max_freq), in intel_rps_enable()
1578 rps->power.up_threshold, in intel_rps_enable()
1579 rps->power.down_threshold); in intel_rps_enable()
1581 GEM_BUG_ON(rps->max_freq < rps->min_freq); in intel_rps_enable()
1582 GEM_BUG_ON(rps->idle_freq > rps->max_freq); in intel_rps_enable()
1584 GEM_BUG_ON(rps->efficient_freq < rps->min_freq); in intel_rps_enable()
1585 GEM_BUG_ON(rps->efficient_freq > rps->max_freq); in intel_rps_enable()
1622 * N = val - 0xb7 in byt_gpu_freq()
1625 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); in byt_gpu_freq()
1630 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; in byt_freq_opcode()
1639 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); in chv_gpu_freq()
1645 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; in chv_freq_opcode()
1686 rps->gpll_ref_freq = in vlv_init_gpll_ref_freq()
1687 vlv_get_cck_clock(&i915->drm, "GPLL ref", in vlv_init_gpll_ref_freq()
1689 i915->czclk_freq); in vlv_init_gpll_ref_freq()
1691 drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n", in vlv_init_gpll_ref_freq()
1692 rps->gpll_ref_freq); in vlv_init_gpll_ref_freq()
1699 vlv_iosf_sb_get(&i915->drm, in vlv_rps_init()
1706 rps->max_freq = vlv_rps_max_freq(rps); in vlv_rps_init()
1707 rps->rp0_freq = rps->max_freq; in vlv_rps_init()
1708 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1709 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); in vlv_rps_init()
1711 rps->efficient_freq = vlv_rps_rpe_freq(rps); in vlv_rps_init()
1712 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1713 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); in vlv_rps_init()
1715 rps->rp1_freq = vlv_rps_guar_freq(rps); in vlv_rps_init()
1716 drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1717 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); in vlv_rps_init()
1719 rps->min_freq = vlv_rps_min_freq(rps); in vlv_rps_init()
1720 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1721 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); in vlv_rps_init()
1723 vlv_iosf_sb_put(&i915->drm, in vlv_rps_init()
1733 vlv_iosf_sb_get(&i915->drm, in chv_rps_init()
1740 rps->max_freq = chv_rps_max_freq(rps); in chv_rps_init()
1741 rps->rp0_freq = rps->max_freq; in chv_rps_init()
1742 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", in chv_rps_init()
1743 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); in chv_rps_init()
1745 rps->efficient_freq = chv_rps_rpe_freq(rps); in chv_rps_init()
1746 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", in chv_rps_init()
1747 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); in chv_rps_init()
1749 rps->rp1_freq = chv_rps_guar_freq(rps); in chv_rps_init()
1750 drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n", in chv_rps_init()
1751 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); in chv_rps_init()
1753 rps->min_freq = chv_rps_min_freq(rps); in chv_rps_init()
1754 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", in chv_rps_init()
1755 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); in chv_rps_init()
1757 vlv_iosf_sb_put(&i915->drm, in chv_rps_init()
1762 drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq | in chv_rps_init()
1763 rps->rp1_freq | rps->min_freq) & 1, in chv_rps_init()
1769 ei->ktime = ktime_get_raw(); in vlv_c0_read()
1770 ei->render_c0 = intel_uncore_read(uncore, VLV_RENDER_C0_COUNT); in vlv_c0_read()
1771 ei->media_c0 = intel_uncore_read(uncore, VLV_MEDIA_C0_COUNT); in vlv_c0_read()
1777 const struct intel_rps_ei *prev = &rps->ei; in vlv_wa_c0_ei()
1786 if (prev->ktime) { in vlv_wa_c0_ei()
1790 time = ktime_us_delta(now.ktime, prev->ktime); in vlv_wa_c0_ei()
1792 time *= rps_to_i915(rps)->czclk_freq; in vlv_wa_c0_ei()
1799 render = now.render_c0 - prev->render_c0; in vlv_wa_c0_ei()
1800 media = now.media_c0 - prev->media_c0; in vlv_wa_c0_ei()
1804 if (c0 > time * rps->power.up_threshold) in vlv_wa_c0_ei()
1806 else if (c0 < time * rps->power.down_threshold) in vlv_wa_c0_ei()
1810 rps->ei = now; in vlv_wa_c0_ei()
1823 spin_lock_irq(gt->irq_lock); in rps_work()
1824 pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events; in rps_work()
1825 client_boost = atomic_read(&rps->num_waiters); in rps_work()
1826 spin_unlock_irq(gt->irq_lock); in rps_work()
1832 mutex_lock(&rps->lock); in rps_work()
1834 mutex_unlock(&rps->lock); in rps_work()
1840 adj = rps->last_adj; in rps_work()
1841 new_freq = rps->cur_freq; in rps_work()
1842 min = rps->min_freq_softlimit; in rps_work()
1843 max = rps->max_freq_softlimit; in rps_work()
1845 max = rps->max_freq; in rps_work()
1852 if (client_boost && new_freq < rps->boost_freq) { in rps_work()
1853 new_freq = rps->boost_freq; in rps_work()
1859 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; in rps_work()
1861 if (new_freq >= rps->max_freq_softlimit) in rps_work()
1866 if (rps->cur_freq > rps->efficient_freq) in rps_work()
1867 new_freq = rps->efficient_freq; in rps_work()
1868 else if (rps->cur_freq > rps->min_freq_softlimit) in rps_work()
1869 new_freq = rps->min_freq_softlimit; in rps_work()
1875 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; in rps_work()
1877 if (new_freq <= rps->min_freq_softlimit) in rps_work()
1891 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n"); in rps_work()
1894 rps->last_adj = adj; in rps_work()
1896 mutex_unlock(&rps->lock); in rps_work()
1899 spin_lock_irq(gt->irq_lock); in rps_work()
1900 gen6_gt_pm_unmask_irq(gt, rps->pm_events); in rps_work()
1901 spin_unlock_irq(gt->irq_lock); in rps_work()
1907 const u32 events = rps->pm_events & pm_iir; in gen11_rps_irq_handler()
1909 lockdep_assert_held(gt->irq_lock); in gen11_rps_irq_handler()
1918 rps->pm_iir |= events; in gen11_rps_irq_handler()
1919 queue_work(gt->i915->unordered_wq, &rps->work); in gen11_rps_irq_handler()
1927 events = pm_iir & rps->pm_events; in gen6_rps_irq_handler()
1929 spin_lock(gt->irq_lock); in gen6_rps_irq_handler()
1934 rps->pm_iir |= events; in gen6_rps_irq_handler()
1936 queue_work(gt->i915->unordered_wq, &rps->work); in gen6_rps_irq_handler()
1937 spin_unlock(gt->irq_lock); in gen6_rps_irq_handler()
1940 if (GRAPHICS_VER(gt->i915) >= 8) in gen6_rps_irq_handler()
1944 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); in gen6_rps_irq_handler()
1947 drm_dbg(&rps_to_i915(rps)->drm, in gen6_rps_irq_handler()
1970 new_freq = rps->cur_freq; in gen5_rps_irq_handler()
1974 new_freq--; in gen5_rps_irq_handler()
1976 rps->min_freq_softlimit, in gen5_rps_irq_handler()
1977 rps->max_freq_softlimit); in gen5_rps_irq_handler()
1979 if (new_freq != rps->cur_freq && !__gen5_rps_set(rps, new_freq)) in gen5_rps_irq_handler()
1980 rps->cur_freq = new_freq; in gen5_rps_irq_handler()
1987 mutex_init(&rps->lock); in intel_rps_init_early()
1988 mutex_init(&rps->power.mutex); in intel_rps_init_early()
1990 INIT_WORK(&rps->work, rps_work); in intel_rps_init_early()
1991 timer_setup(&rps->timer, rps_timer, 0); in intel_rps_init_early()
1993 atomic_set(&rps->num_waiters, 0); in intel_rps_init_early()
2013 rps->max_freq_softlimit = rps->max_freq; in intel_rps_init()
2014 rps_to_gt(rps)->defaults.max_freq = rps->max_freq_softlimit; in intel_rps_init()
2015 rps->min_freq_softlimit = rps->min_freq; in intel_rps_init()
2016 rps_to_gt(rps)->defaults.min_freq = rps->min_freq_softlimit; in intel_rps_init()
2018 /* After setting max-softlimit, find the overclock max freq */ in intel_rps_init()
2022 snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, ¶ms, NULL); in intel_rps_init()
2024 drm_dbg(&i915->drm, in intel_rps_init()
2026 (rps->max_freq & 0xff) * 50, in intel_rps_init()
2028 rps->max_freq = params & 0xff; in intel_rps_init()
2033 rps->power.up_threshold = 95; in intel_rps_init()
2034 rps_to_gt(rps)->defaults.rps_up_threshold = rps->power.up_threshold; in intel_rps_init()
2035 rps->power.down_threshold = 85; in intel_rps_init()
2036 rps_to_gt(rps)->defaults.rps_down_threshold = rps->power.down_threshold; in intel_rps_init()
2039 rps->boost_freq = rps->max_freq; in intel_rps_init()
2040 rps->idle_freq = rps->min_freq; in intel_rps_init()
2043 rps->cur_freq = rps->efficient_freq; in intel_rps_init()
2045 rps->pm_intrmsk_mbz = 0; in intel_rps_init()
2054 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; in intel_rps_init()
2057 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; in intel_rps_init()
2060 if (intel_uc_uses_guc_submission(&rps_to_gt(rps)->uc)) in intel_rps_init()
2061 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; in intel_rps_init()
2080 return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); in intel_rps_read_rpstat()
2122 vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in __read_cagf()
2123 freq = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); in __read_cagf()
2124 vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); in __read_cagf()
2144 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; in intel_rps_read_actual_frequency()
2162 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; in intel_rps_read_punit_req()
2191 return intel_gpu_freq(rps, rps->cur_freq); in intel_rps_get_requested_frequency()
2199 return slpc->max_freq_softlimit; in intel_rps_get_max_frequency()
2201 return intel_gpu_freq(rps, rps->max_freq_softlimit); in intel_rps_get_max_frequency()
2205 * intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
2217 return DIV_ROUND_CLOSEST(slpc->rp0_freq, in intel_rps_get_max_raw_freq()
2220 freq = rps->max_freq; in intel_rps_get_max_raw_freq()
2234 return slpc->rp0_freq; in intel_rps_get_rp0_frequency()
2236 return intel_gpu_freq(rps, rps->rp0_freq); in intel_rps_get_rp0_frequency()
2244 return slpc->rp1_freq; in intel_rps_get_rp1_frequency()
2246 return intel_gpu_freq(rps, rps->rp1_freq); in intel_rps_get_rp1_frequency()
2254 return slpc->min_freq; in intel_rps_get_rpn_frequency()
2256 return intel_gpu_freq(rps, rps->min_freq); in intel_rps_get_rpn_frequency()
2262 struct drm_i915_private *i915 = gt->i915; in rps_frequency_dump()
2263 struct intel_uncore *uncore = gt->uncore; in rps_frequency_dump()
2353 rps->pm_intrmsk_mbz); in rps_frequency_dump()
2355 drm_printf(p, "Render p-state ratio: %d\n", in rps_frequency_dump()
2357 drm_printf(p, "Render p-state VID: %d\n", in rps_frequency_dump()
2359 drm_printf(p, "Render p-state limit: %d\n", in rps_frequency_dump()
2375 rps->power.up_threshold); in rps_frequency_dump()
2391 rps->power.down_threshold); in rps_frequency_dump()
2399 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", in rps_frequency_dump()
2401 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", in rps_frequency_dump()
2404 intel_gpu_freq(rps, rps->max_freq)); in rps_frequency_dump()
2407 intel_gpu_freq(rps, rps->cur_freq)); in rps_frequency_dump()
2410 intel_gpu_freq(rps, rps->idle_freq)); in rps_frequency_dump()
2412 intel_gpu_freq(rps, rps->min_freq)); in rps_frequency_dump()
2414 intel_gpu_freq(rps, rps->boost_freq)); in rps_frequency_dump()
2416 intel_gpu_freq(rps, rps->max_freq)); in rps_frequency_dump()
2419 intel_gpu_freq(rps, rps->efficient_freq)); in rps_frequency_dump()
2425 struct intel_uncore *uncore = gt->uncore; in slpc_frequency_dump()
2434 rps->pm_intrmsk_mbz); in slpc_frequency_dump()
2439 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", in slpc_frequency_dump()
2441 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", in slpc_frequency_dump()
2471 mutex_lock(&rps->lock); in set_max_freq()
2474 if (val < rps->min_freq || in set_max_freq()
2475 val > rps->max_freq || in set_max_freq()
2476 val < rps->min_freq_softlimit) { in set_max_freq()
2477 ret = -EINVAL; in set_max_freq()
2481 if (val > rps->rp0_freq) in set_max_freq()
2482 drm_dbg(&i915->drm, "User requested overclocking to %d\n", in set_max_freq()
2485 rps->max_freq_softlimit = val; in set_max_freq()
2487 val = clamp_t(int, rps->cur_freq, in set_max_freq()
2488 rps->min_freq_softlimit, in set_max_freq()
2489 rps->max_freq_softlimit); in set_max_freq()
2499 mutex_unlock(&rps->lock); in set_max_freq()
2519 return slpc->min_freq_softlimit; in intel_rps_get_min_frequency()
2521 return intel_gpu_freq(rps, rps->min_freq_softlimit); in intel_rps_get_min_frequency()
2525 * intel_rps_get_min_raw_freq - returns the min frequency in some raw format.
2537 return DIV_ROUND_CLOSEST(slpc->min_freq, in intel_rps_get_min_raw_freq()
2540 freq = rps->min_freq; in intel_rps_get_min_raw_freq()
2553 mutex_lock(&rps->lock); in set_min_freq()
2556 if (val < rps->min_freq || in set_min_freq()
2557 val > rps->max_freq || in set_min_freq()
2558 val > rps->max_freq_softlimit) { in set_min_freq()
2559 ret = -EINVAL; in set_min_freq()
2563 rps->min_freq_softlimit = val; in set_min_freq()
2565 val = clamp_t(int, rps->cur_freq, in set_min_freq()
2566 rps->min_freq_softlimit, in set_min_freq()
2567 rps->max_freq_softlimit); in set_min_freq()
2577 mutex_unlock(&rps->lock); in set_min_freq()
2594 return rps->power.up_threshold; in intel_rps_get_up_threshold()
2602 return -EINVAL; in rps_set_threshold()
2604 ret = mutex_lock_interruptible(&rps->lock); in rps_set_threshold()
2614 rps->last_freq = -1; in rps_set_threshold()
2615 mutex_lock(&rps->power.mutex); in rps_set_threshold()
2616 rps->power.mode = -1; in rps_set_threshold()
2617 mutex_unlock(&rps->power.mutex); in rps_set_threshold()
2619 intel_rps_set(rps, clamp(rps->cur_freq, in rps_set_threshold()
2620 rps->min_freq_softlimit, in rps_set_threshold()
2621 rps->max_freq_softlimit)); in rps_set_threshold()
2624 mutex_unlock(&rps->lock); in rps_set_threshold()
2631 return rps_set_threshold(rps, &rps->power.up_threshold, threshold); in intel_rps_set_up_threshold()
2636 return rps->power.down_threshold; in intel_rps_get_down_threshold()
2641 return rps_set_threshold(rps, &rps->power.down_threshold, threshold); in intel_rps_set_down_threshold()
2657 mutex_lock(&rps->lock); in intel_rps_raise_unslice()
2672 intel_rps_set(rps, rps->rp0_freq); in intel_rps_raise_unslice()
2675 mutex_unlock(&rps->lock); in intel_rps_raise_unslice()
2682 mutex_lock(&rps->lock); in intel_rps_lower_unslice()
2697 intel_rps_set(rps, rps->min_freq); in intel_rps_lower_unslice()
2700 mutex_unlock(&rps->lock); in intel_rps_lower_unslice()
2709 with_intel_runtime_pm(gt->uncore->rpm, wakeref) in rps_read_mmio()
2710 val = intel_uncore_read(gt->uncore, reg32); in rps_read_mmio()
2750 * We only register the i915 ips part with intel-ips once everything is in intel_rps_driver_register()
2751 * set up, to avoid intel-ips sneaking in and reading bogus values. in intel_rps_driver_register()
2753 if (GRAPHICS_VER(gt->i915) == 5) { in intel_rps_driver_register()
2755 rcu_assign_pointer(ips_mchdev, gt->i915); in intel_rps_driver_register()
2772 if (i915 && !kref_get_unless_zero(&i915->drm.ref)) in mchdev_get()
2780 * i915_read_mch_val - return value for IPS use
2796 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { in i915_read_mch_val()
2797 struct intel_ips *ips = &to_gt(i915)->rps.ips; in i915_read_mch_val()
2805 drm_dev_put(&i915->drm); in i915_read_mch_val()
2811 * i915_gpu_raise - raise GPU frequency limit
2824 rps = &to_gt(i915)->rps; in i915_gpu_raise()
2827 if (rps->max_freq_softlimit < rps->max_freq) in i915_gpu_raise()
2828 rps->max_freq_softlimit++; in i915_gpu_raise()
2831 drm_dev_put(&i915->drm); in i915_gpu_raise()
2837 * i915_gpu_lower - lower GPU frequency limit
2851 rps = &to_gt(i915)->rps; in i915_gpu_lower()
2854 if (rps->max_freq_softlimit > rps->min_freq) in i915_gpu_lower()
2855 rps->max_freq_softlimit--; in i915_gpu_lower()
2858 drm_dev_put(&i915->drm); in i915_gpu_lower()
2864 * i915_gpu_busy - indicate GPU business to IPS
2877 ret = to_gt(i915)->awake; in i915_gpu_busy()
2879 drm_dev_put(&i915->drm); in i915_gpu_busy()
2885 * i915_gpu_turbo_disable - disable graphics turbo
2900 rps = &to_gt(i915)->rps; in i915_gpu_turbo_disable()
2903 rps->max_freq_softlimit = rps->min_freq; in i915_gpu_turbo_disable()
2904 ret = !__gen5_rps_set(&to_gt(i915)->rps, rps->min_freq); in i915_gpu_turbo_disable()
2907 drm_dev_put(&i915->drm); in i915_gpu_turbo_disable()