323 	struct intel_engine_cs *engine;  in __gen6_reset_engines()  local
332 		for_each_engine_masked(engine, gt, engine_mask, tmp) {  in __gen6_reset_engines()
333 			hw_mask |= engine->reset_domain;  in __gen6_reset_engines()
354 static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)  in find_sfc_paired_vecs_engine()  argument
358 	GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);  in find_sfc_paired_vecs_engine()
360 	vecs_id = _VECS((engine->instance) / 2);  in find_sfc_paired_vecs_engine()
362 	return engine->gt->engine[vecs_id];  in find_sfc_paired_vecs_engine()
375 static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,  in get_sfc_forced_lock_data()  argument
378 	switch (engine->class) {  in get_sfc_forced_lock_data()
380 		MISSING_CASE(engine->class);  in get_sfc_forced_lock_data()
383 		sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base);  in get_sfc_forced_lock_data()
386 		sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);  in get_sfc_forced_lock_data()
389 		sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);  in get_sfc_forced_lock_data()
391 		sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);  in get_sfc_forced_lock_data()
395 		sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base);  in get_sfc_forced_lock_data()
398 		sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base);  in get_sfc_forced_lock_data()
401 		sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base);  in get_sfc_forced_lock_data()
403 		sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);  in get_sfc_forced_lock_data()
409 static int gen11_lock_sfc(struct intel_engine_cs *engine,  in gen11_lock_sfc()  argument
413 	struct intel_uncore *uncore = engine->uncore;  in gen11_lock_sfc()
414 	u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;  in gen11_lock_sfc()
419 	switch (engine->class) {  in gen11_lock_sfc()
421 		if ((BIT(engine->instance) & vdbox_sfc_access) == 0)  in gen11_lock_sfc()
426 		get_sfc_forced_lock_data(engine, &sfc_lock);  in gen11_lock_sfc()
436 		if (engine->class != VIDEO_DECODE_CLASS ||  in gen11_lock_sfc()
437 		    GRAPHICS_VER(engine->i915) != 12)  in gen11_lock_sfc()
448 					   GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) &  in gen11_lock_sfc()
452 		paired_vecs = find_sfc_paired_vecs_engine(engine);  in gen11_lock_sfc()
457 		*unlock_mask |= engine->mask;  in gen11_lock_sfc()
493 		ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");  in gen11_lock_sfc()
501 static void gen11_unlock_sfc(struct intel_engine_cs *engine)  in gen11_unlock_sfc()  argument
503 	struct intel_uncore *uncore = engine->uncore;  in gen11_unlock_sfc()
504 	u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;  in gen11_unlock_sfc()
507 	if (engine->class != VIDEO_DECODE_CLASS &&  in gen11_unlock_sfc()
508 	    engine->class != VIDEO_ENHANCEMENT_CLASS)  in gen11_unlock_sfc()
511 	if (engine->class == VIDEO_DECODE_CLASS &&  in gen11_unlock_sfc()
512 	    (BIT(engine->instance) & vdbox_sfc_access) == 0)  in gen11_unlock_sfc()
515 	get_sfc_forced_lock_data(engine, &sfc_lock);  in gen11_unlock_sfc()
524 	struct intel_engine_cs *engine;  in __gen11_reset_engines()  local
533 		for_each_engine_masked(engine, gt, engine_mask, tmp) {  in __gen11_reset_engines()
534 			reset_mask |= engine->reset_domain;  in __gen11_reset_engines()
535 			ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);  in __gen11_reset_engines()
555 	for_each_engine_masked(engine, gt, unlock_mask, tmp)  in __gen11_reset_engines()
556 		gen11_unlock_sfc(engine);  in __gen11_reset_engines()
561 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)  in gen8_engine_reset_prepare()  argument
563 	struct intel_uncore *uncore = engine->uncore;  in gen8_engine_reset_prepare()
564 	const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);  in gen8_engine_reset_prepare()
568 	if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))  in gen8_engine_reset_prepare()
594 		gt_err(engine->gt,  in gen8_engine_reset_prepare()
596 		       engine->name, request,  in gen8_engine_reset_prepare()
602 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)  in gen8_engine_reset_cancel()  argument
604 	intel_uncore_write_fw(engine->uncore,  in gen8_engine_reset_cancel()
605 			      RING_RESET_CTL(engine->mmio_base),  in gen8_engine_reset_cancel()
613 	struct intel_engine_cs *engine;  in gen8_reset_engines()  local
621 	for_each_engine_masked(engine, gt, engine_mask, tmp) {  in gen8_reset_engines()
622 		ret = gen8_engine_reset_prepare(engine);  in gen8_reset_engines()
656 	for_each_engine_masked(engine, gt, engine_mask, tmp)  in gen8_reset_engines()
657 		gen8_engine_reset_cancel(engine);  in gen8_reset_engines()
736 	if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) {  in wa_14015076503_start()
829 static void reset_prepare_engine(struct intel_engine_cs *engine)  in reset_prepare_engine()  argument
838 	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);  in reset_prepare_engine()
839 	if (engine->reset.prepare)  in reset_prepare_engine()
840 		engine->reset.prepare(engine);  in reset_prepare_engine()
876 	struct intel_engine_cs *engine;  in reset_prepare()  local
892 	for_each_engine(engine, gt, id) {  in reset_prepare()
893 		if (intel_engine_pm_get_if_awake(engine))  in reset_prepare()
894 			awake |= engine->mask;  in reset_prepare()
895 		reset_prepare_engine(engine);  in reset_prepare()
908 	struct intel_engine_cs *engine;  in gt_reset()  local
921 	for_each_engine(engine, gt, id)  in gt_reset()
922 		__intel_engine_reset(engine, stalled_mask & engine->mask);  in gt_reset()
932 static void reset_finish_engine(struct intel_engine_cs *engine)  in reset_finish_engine()  argument
934 	if (engine->reset.finish)  in reset_finish_engine()
935 		engine->reset.finish(engine);  in reset_finish_engine()
936 	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);  in reset_finish_engine()
938 	intel_engine_signal_breadcrumbs(engine);  in reset_finish_engine()
943 	struct intel_engine_cs *engine;  in reset_finish()  local
946 	for_each_engine(engine, gt, id) {  in reset_finish()
947 		reset_finish_engine(engine);  in reset_finish()
948 		if (awake & engine->mask)  in reset_finish()
949 			intel_engine_pm_put(engine);  in reset_finish()
962 		intel_engine_signal_breadcrumbs(request->engine);  in nop_submit_request()
970 	struct intel_engine_cs *engine;  in __intel_gt_set_wedged()  local
990 	for_each_engine(engine, gt, id)  in __intel_gt_set_wedged()
991 		engine->submit_request = nop_submit_request;  in __intel_gt_set_wedged()
1003 	for_each_engine(engine, gt, id)  in __intel_gt_set_wedged()
1004 		if (engine->reset.cancel)  in __intel_gt_set_wedged()
1005 			engine->reset.cancel(engine);  in __intel_gt_set_wedged()
1036 		struct intel_engine_cs *engine;  in intel_gt_set_wedged()  local
1040 		for_each_engine(engine, gt, id) {  in intel_gt_set_wedged()
1041 			if (intel_engine_is_idle(engine))  in intel_gt_set_wedged()
1044 			intel_engine_dump(engine, &p, "%s\n", engine->name);  in intel_gt_set_wedged()
1165 	struct intel_engine_cs *engine;  in resume()  local
1169 	for_each_engine(engine, gt, id) {  in resume()
1170 		ret = intel_engine_resume(engine);  in resume()
1323 int intel_gt_reset_engine(struct intel_engine_cs *engine)  in intel_gt_reset_engine()  argument
1325 	return __intel_gt_reset(engine->gt, engine->mask);  in intel_gt_reset_engine()
1328 int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)  in __intel_engine_reset_bh()  argument
1330 	struct intel_gt *gt = engine->gt;  in __intel_engine_reset_bh()
1333 	ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);  in __intel_engine_reset_bh()
1334 	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));  in __intel_engine_reset_bh()
1336 	if (intel_engine_uses_guc(engine))  in __intel_engine_reset_bh()
1339 	if (!intel_engine_pm_get_if_awake(engine))  in __intel_engine_reset_bh()
1342 	reset_prepare_engine(engine);  in __intel_engine_reset_bh()
1345 		drm_notice(&engine->i915->drm,  in __intel_engine_reset_bh()
1346 			   "Resetting %s for %s\n", engine->name, msg);  in __intel_engine_reset_bh()
1347 	i915_increase_reset_engine_count(&engine->i915->gpu_error, engine);  in __intel_engine_reset_bh()
1349 	ret = intel_gt_reset_engine(engine);  in __intel_engine_reset_bh()
1352 		ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);  in __intel_engine_reset_bh()
1361 	__intel_engine_reset(engine, true);  in __intel_engine_reset_bh()
1368 	ret = intel_engine_resume(engine);  in __intel_engine_reset_bh()
1371 	intel_engine_cancel_stop_cs(engine);  in __intel_engine_reset_bh()
1372 	reset_finish_engine(engine);  in __intel_engine_reset_bh()
1373 	intel_engine_pm_put_async(engine);  in __intel_engine_reset_bh()
1390 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)  in intel_engine_reset()  argument
1395 	err = __intel_engine_reset_bh(engine, msg);  in intel_engine_reset()
1471 	struct intel_engine_cs *engine;  in intel_gt_handle_error()  local
1510 		for_each_engine_masked(engine, gt, engine_mask, tmp) {  in intel_gt_handle_error()
1512 			if (test_and_set_bit(I915_RESET_ENGINE + engine->id,  in intel_gt_handle_error()
1516 			if (__intel_engine_reset_bh(engine, msg) == 0)  in intel_gt_handle_error()
1517 				engine_mask &= ~engine->mask;  in intel_gt_handle_error()
1519 			clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,  in intel_gt_handle_error()
1543 		for_each_engine(engine, gt, tmp) {  in intel_gt_handle_error()
1544 			while (test_and_set_bit(I915_RESET_ENGINE + engine->id,  in intel_gt_handle_error()
1547 					    I915_RESET_ENGINE + engine->id,  in intel_gt_handle_error()
1558 		for_each_engine(engine, gt, tmp)  in intel_gt_handle_error()
1559 			clear_bit_unlock(I915_RESET_ENGINE + engine->id,  in intel_gt_handle_error()