Lines Matching +full:reset +full:- +full:mask
1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2018 Intel Corporation
41 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
52 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
57 atomic_add(score, &file_priv->ban_score); in client_mark_guilty()
59 drm_dbg(&ctx->i915->drm, in client_mark_guilty()
61 ctx->name, score, in client_mark_guilty()
62 atomic_read(&file_priv->ban_score)); in client_mark_guilty()
73 if (intel_context_is_closed(rq->context)) in mark_guilty()
77 ctx = rcu_dereference(rq->context->gem_context); in mark_guilty()
78 if (ctx && !kref_get_unless_zero(&ctx->ref)) in mark_guilty()
82 return intel_context_is_banned(rq->context); in mark_guilty()
84 atomic_inc(&ctx->guilty_count); in mark_guilty()
86 /* Cool contexts are too cool to be banned! (Used for reset testing.) */ in mark_guilty()
92 drm_notice(&ctx->i915->drm, in mark_guilty()
93 "%s context reset due to GPU hang\n", in mark_guilty()
94 ctx->name); in mark_guilty()
97 prev_hang = ctx->hang_timestamp[0]; in mark_guilty()
98 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++) in mark_guilty()
99 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1]; in mark_guilty()
100 ctx->hang_timestamp[i] = jiffies; in mark_guilty()
107 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n", in mark_guilty()
108 ctx->name, atomic_read(&ctx->guilty_count)); in mark_guilty()
122 ctx = rcu_dereference(rq->context->gem_context); in mark_innocent()
124 atomic_inc(&ctx->active_count); in mark_innocent()
137 i915_request_set_error_once(rq, -EIO); in __i915_request_reset()
141 i915_request_set_error_once(rq, -EAGAIN); in __i915_request_reset()
147 intel_context_ban(rq->context, rq); in __i915_request_reset()
162 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev); in i915_do_reset()
165 /* Assert reset for at least 50 usec, and wait for acknowledgement. */ in i915_do_reset()
170 /* Clear the reset request. */ in i915_do_reset()
191 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev); in g33_do_reset()
201 struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev); in g4x_do_reset()
202 struct intel_uncore *uncore = gt->uncore; in g4x_do_reset()
213 GT_TRACE(gt, "Wait for media reset failed\n"); in g4x_do_reset()
221 GT_TRACE(gt, "Wait for render reset failed\n"); in g4x_do_reset()
237 struct intel_uncore *uncore = gt->uncore; in ilk_do_reset()
247 GT_TRACE(gt, "Wait for render reset failed\n"); in ilk_do_reset()
258 GT_TRACE(gt, "Wait for media reset failed\n"); in ilk_do_reset()
268 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
271 struct intel_uncore *uncore = gt->uncore; in gen6_hw_domain_reset()
279 * state is still in flux. If we immediately repeat the reset, the in gen6_hw_domain_reset()
280 * second reset appears to serialise with the first, and since it is a in gen6_hw_domain_reset()
281 * no-op, the registers should retain their reset value. However, there in gen6_hw_domain_reset()
282 * is still a concern that upon leaving the second reset, the internal in gen6_hw_domain_reset()
289 * observed on MTL, we avoid repeating the reset on newer platforms. in gen6_hw_domain_reset()
291 loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1; in gen6_hw_domain_reset()
301 /* Wait for the device to ack the reset requests. */ in gen6_hw_domain_reset()
306 } while (err == 0 && --loops); in gen6_hw_domain_reset()
309 "Wait for 0x%08x engines reset failed\n", in gen6_hw_domain_reset()
335 hw_mask |= engine->reset_domain; in __gen6_reset_engines()
349 spin_lock_irqsave(>->uncore->lock, flags); in gen6_reset_engines()
351 spin_unlock_irqrestore(>->uncore->lock, flags); in gen6_reset_engines()
360 GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS); in find_sfc_paired_vecs_engine()
362 vecs_id = _VECS((engine->instance) / 2); in find_sfc_paired_vecs_engine()
364 return engine->gt->engine[vecs_id]; in find_sfc_paired_vecs_engine()
380 switch (engine->class) { in get_sfc_forced_lock_data()
382 MISSING_CASE(engine->class); in get_sfc_forced_lock_data()
385 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base); in get_sfc_forced_lock_data()
386 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT; in get_sfc_forced_lock_data()
388 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base); in get_sfc_forced_lock_data()
389 sfc_lock->ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT; in get_sfc_forced_lock_data()
391 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base); in get_sfc_forced_lock_data()
392 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT; in get_sfc_forced_lock_data()
393 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance); in get_sfc_forced_lock_data()
397 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base); in get_sfc_forced_lock_data()
398 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT; in get_sfc_forced_lock_data()
400 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base); in get_sfc_forced_lock_data()
401 sfc_lock->ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT; in get_sfc_forced_lock_data()
403 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base); in get_sfc_forced_lock_data()
404 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT; in get_sfc_forced_lock_data()
405 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance); in get_sfc_forced_lock_data()
415 struct intel_uncore *uncore = engine->uncore; in gen11_lock_sfc()
416 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; in gen11_lock_sfc()
421 switch (engine->class) { in gen11_lock_sfc()
423 if ((BIT(engine->instance) & vdbox_sfc_access) == 0) in gen11_lock_sfc()
438 if (engine->class != VIDEO_DECODE_CLASS || in gen11_lock_sfc()
439 GRAPHICS_VER(engine->i915) != 12) in gen11_lock_sfc()
445 * If the VCS-MFX isn't using the SFC, we also need to check in gen11_lock_sfc()
446 * whether VCS-HCP is using it. If so, we need to issue a *VE* in gen11_lock_sfc()
450 GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) & in gen11_lock_sfc()
457 *unlock_mask |= paired_vecs->mask; in gen11_lock_sfc()
459 *unlock_mask |= engine->mask; in gen11_lock_sfc()
463 * If the engine is using an SFC, tell the engine that a software reset in gen11_lock_sfc()
465 * If SFC ends up being locked to the engine we want to reset, we have in gen11_lock_sfc()
466 * to reset it as well (we will unlock it once the reset sequence is in gen11_lock_sfc()
480 * We should reset both the engine and the SFC if: in gen11_lock_sfc()
481 * - We were locking the SFC to this engine and the lock succeeded in gen11_lock_sfc()
483 * - We were locking the SFC to a different engine (Wa_14010733141) in gen11_lock_sfc()
486 * Otherwise we need only reset the engine by itself and we can in gen11_lock_sfc()
505 struct intel_uncore *uncore = engine->uncore; in gen11_unlock_sfc()
506 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; in gen11_unlock_sfc()
509 if (engine->class != VIDEO_DECODE_CLASS && in gen11_unlock_sfc()
510 engine->class != VIDEO_ENHANCEMENT_CLASS) in gen11_unlock_sfc()
513 if (engine->class == VIDEO_DECODE_CLASS && in gen11_unlock_sfc()
514 (BIT(engine->instance) & vdbox_sfc_access) == 0) in gen11_unlock_sfc()
536 reset_mask |= engine->reset_domain; in __gen11_reset_engines()
553 * wasn't being reset. So instead of calling gen11_unlock_sfc() in __gen11_reset_engines()
554 * on engine_mask, we instead call it on the mask of engines that our in __gen11_reset_engines()
565 struct intel_uncore *uncore = engine->uncore; in gen8_engine_reset_prepare()
566 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); in gen8_engine_reset_prepare()
567 u32 request, mask, ack; in gen8_engine_reset_prepare() local
570 if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1))) in gen8_engine_reset_prepare()
571 return -ETIMEDOUT; in gen8_engine_reset_prepare()
576 * For catastrophic errors, ready-for-reset sequence in gen8_engine_reset_prepare()
580 mask = RESET_CTL_CAT_ERROR; in gen8_engine_reset_prepare()
586 mask = RESET_CTL_READY_TO_RESET; in gen8_engine_reset_prepare()
593 ret = __intel_wait_for_register_fw(uncore, reg, mask, ack, in gen8_engine_reset_prepare()
596 gt_err(engine->gt, in gen8_engine_reset_prepare()
597 "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n", in gen8_engine_reset_prepare()
598 engine->name, request, in gen8_engine_reset_prepare()
606 intel_uncore_write_fw(engine->uncore, in gen8_engine_reset_cancel()
607 RING_RESET_CTL(engine->mmio_base), in gen8_engine_reset_cancel()
621 spin_lock_irqsave(>->uncore->lock, flags); in gen8_reset_engines()
633 * some gens (kbl), possible system hang if reset in gen8_reset_engines()
637 * failed reset with a wedged driver/gpu. And in gen8_reset_engines()
639 * stop_engines() we have before the reset. in gen8_reset_engines()
644 * Wa_22011100796:dg2, whenever Full soft reset is required, in gen8_reset_engines()
645 * reset all individual engines firstly, and then do a full soft reset. in gen8_reset_engines()
647 * This is best effort, so ignore any error from the initial reset. in gen8_reset_engines()
649 if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES) in gen8_reset_engines()
650 __gen11_reset_engines(gt, gt->info.engine_mask, 0); in gen8_reset_engines()
652 if (GRAPHICS_VER(gt->i915) >= 11) in gen8_reset_engines()
661 spin_unlock_irqrestore(>->uncore->lock, flags); in gen8_reset_engines()
667 intel_engine_mask_t mask, in mock_reset() argument
679 struct drm_i915_private *i915 = gt->i915; in intel_get_gpu_reset()
702 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC; in __reset_guc()
709 if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0)) in needs_wa_14015076503()
715 return intel_gsc_uc_fw_init_done(>->uc.gsc); in needs_wa_14015076503()
726 * we're going to do a GSC engine reset and then wait for 200ms for the in wa_14015076503_start()
728 * reset attempt and the GSC is not busy, we can try to instead reset in wa_14015076503_start()
734 * it has no state that we don't explicitly re-init on resume or on in wa_14015076503_start()
738 if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) { in wa_14015076503_start()
740 engine_mask = gt->info.engine_mask & ~BIT(GSC0); in wa_14015076503_start()
742 intel_uncore_rmw(gt->uncore, in wa_14015076503_start()
746 /* make sure the reset bit is clear when writing the CSR reg */ in wa_14015076503_start()
747 intel_uncore_rmw(gt->uncore, in wa_14015076503_start()
762 intel_uncore_rmw(gt->uncore, in wa_14015076503_end()
770 reset_func reset; in __intel_gt_reset() local
771 int ret = -ETIMEDOUT; in __intel_gt_reset()
774 reset = intel_get_gpu_reset(gt); in __intel_gt_reset()
775 if (!reset) in __intel_gt_reset()
776 return -ENODEV; in __intel_gt_reset()
779 * If the power well sleeps during the reset, the reset in __intel_gt_reset()
780 * request may be dropped and never completes (causing -EIO). in __intel_gt_reset()
782 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in __intel_gt_reset()
783 for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) { in __intel_gt_reset()
789 ret = reset(gt, reset_mask, retry); in __intel_gt_reset()
793 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); in __intel_gt_reset()
800 if (!gt->i915->params.reset) in intel_has_gpu_reset()
808 if (gt->i915->params.reset < 2) in intel_has_reset_engine()
811 return INTEL_INFO(gt->i915)->has_reset_engine; in intel_has_reset_engine()
818 GEM_BUG_ON(!HAS_GT_UC(gt->i915)); in intel_reset_guc()
820 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); in intel_reset_guc()
822 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); in intel_reset_guc()
834 * During the reset sequence, we must prevent the engine from in reset_prepare_engine()
836 * the engine, if it does enter RC6 during the reset, the state in reset_prepare_engine()
838 * GPU state upon resume, i.e. fail to restart after a reset. in reset_prepare_engine()
840 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); in reset_prepare_engine()
841 if (engine->reset.prepare) in reset_prepare_engine()
842 engine->reset.prepare(engine); in reset_prepare_engine()
849 for (i = 0; i < gt->ggtt->num_fences; i++) { in revoke_mmaps()
854 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma); in revoke_mmaps()
861 GEM_BUG_ON(vma->fence != >->ggtt->fence_regs[i]); in revoke_mmaps()
863 if (!vma->mmo) in revoke_mmaps()
866 node = &vma->mmo->vma_node; in revoke_mmaps()
867 vma_offset = vma->gtt_view.partial.offset << PAGE_SHIFT; in revoke_mmaps()
869 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping, in revoke_mmaps()
871 vma->size, in revoke_mmaps()
887 * sanitized, do that after engine reset. reset_prepare() in reset_prepare()
888 * is followed by engine reset which in this mode requires GuC to in reset_prepare()
891 if (intel_uc_uses_guc_submission(>->uc)) in reset_prepare()
892 intel_uc_reset_prepare(>->uc); in reset_prepare()
896 awake |= engine->mask; in reset_prepare()
918 err = i915_ggtt_enable_hw(gt->i915); in gt_reset()
924 __intel_engine_reset(engine, stalled_mask & engine->mask); in gt_reset()
927 intel_uc_reset(>->uc, ALL_ENGINES); in gt_reset()
929 intel_ggtt_restore_fences(gt->ggtt); in gt_reset()
936 if (engine->reset.finish) in reset_finish_engine()
937 engine->reset.finish(engine); in reset_finish_engine()
938 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); in reset_finish_engine()
950 if (awake & engine->mask) in reset_finish()
954 intel_uc_reset_finish(>->uc); in reset_finish()
959 RQ_TRACE(request, "-EIO\n"); in nop_submit_request()
964 intel_engine_signal_breadcrumbs(request->engine); in nop_submit_request()
976 if (test_bit(I915_WEDGED, >->reset.flags)) in __intel_gt_set_wedged()
988 /* Even if the GPU reset fails, it should still stop the engines */ in __intel_gt_set_wedged()
989 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) in __intel_gt_set_wedged()
993 engine->submit_request = nop_submit_request; in __intel_gt_set_wedged()
1001 set_bit(I915_WEDGED, >->reset.flags); in __intel_gt_set_wedged()
1006 if (engine->reset.cancel) in __intel_gt_set_wedged()
1007 engine->reset.cancel(engine); in __intel_gt_set_wedged()
1008 intel_uc_cancel_requests(>->uc); in __intel_gt_set_wedged()
1021 with_intel_runtime_pm(gt->uncore->rpm, wf) in set_wedged_work()
1029 if (test_bit(I915_WEDGED, >->reset.flags)) in intel_gt_set_wedged()
1032 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_gt_set_wedged()
1033 mutex_lock(>->reset.mutex); in intel_gt_set_wedged()
1036 struct drm_printer p = drm_dbg_printer(>->i915->drm, in intel_gt_set_wedged()
1046 intel_engine_dump(engine, &p, "%s\n", engine->name); in intel_gt_set_wedged()
1052 mutex_unlock(>->reset.mutex); in intel_gt_set_wedged()
1053 intel_runtime_pm_put(gt->uncore->rpm, wakeref); in intel_gt_set_wedged()
1058 struct intel_gt_timelines *timelines = >->timelines; in __intel_gt_unset_wedged()
1062 if (!test_bit(I915_WEDGED, >->reset.flags)) in __intel_gt_unset_wedged()
1073 * are flushed and errored out - we may have requests waiting upon in __intel_gt_unset_wedged()
1077 * is done inside our nop_submit_request - and so we must wait. in __intel_gt_unset_wedged()
1079 * No more can be submitted until we reset the wedged bit. in __intel_gt_unset_wedged()
1081 spin_lock(&timelines->lock); in __intel_gt_unset_wedged()
1082 list_for_each_entry(tl, &timelines->active_list, link) { in __intel_gt_unset_wedged()
1085 fence = i915_active_fence_get(&tl->last_request); in __intel_gt_unset_wedged()
1089 spin_unlock(&timelines->lock); in __intel_gt_unset_wedged()
1093 * been flushed by the set-wedge, but we may be stuck waiting in __intel_gt_unset_wedged()
1102 spin_lock(&timelines->lock); in __intel_gt_unset_wedged()
1103 tl = list_entry(&timelines->active_list, typeof(*tl), link); in __intel_gt_unset_wedged()
1105 spin_unlock(&timelines->lock); in __intel_gt_unset_wedged()
1107 /* We must reset pending GPU events before restoring our submission */ in __intel_gt_unset_wedged()
1108 ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */ in __intel_gt_unset_wedged()
1109 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) in __intel_gt_unset_wedged()
1116 add_taint_for_CI(gt->i915, TAINT_WARN); in __intel_gt_unset_wedged()
1125 * engine->submit_request() as we swap over. So unlike installing in __intel_gt_unset_wedged()
1126 * the nop_submit_request on reset, we can do this from normal in __intel_gt_unset_wedged()
1134 clear_bit(I915_WEDGED, >->reset.flags); in __intel_gt_unset_wedged()
1143 mutex_lock(>->reset.mutex); in intel_gt_unset_wedged()
1145 mutex_unlock(>->reset.mutex); in intel_gt_unset_wedged()
1181 * intel_gt_reset - reset chip after a hang
1182 * @gt: #intel_gt to reset
1183 * @stalled_mask: mask of the stalled engines with the guilty requests
1186 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1190 * - reset the chip using the reset reg
1191 * - re-init context state
1192 * - re-init hardware status page
1193 * - re-init ring buffer
1194 * - re-init interrupt state
1195 * - re-init display
1204 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags); in intel_gt_reset()
1207 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >->reset.flags)); in intel_gt_reset()
1211 * critical section like gpu reset. in intel_gt_reset()
1215 mutex_lock(>->reset.mutex); in intel_gt_reset()
1223 atomic_inc(>->i915->gpu_error.reset_count); in intel_gt_reset()
1228 if (gt->i915->params.reset) in intel_gt_reset()
1229 gt_err(gt, "GPU reset not supported\n"); in intel_gt_reset()
1231 gt_dbg(gt, "GPU reset disabled\n"); in intel_gt_reset()
1235 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) in intel_gt_reset()
1236 intel_irq_suspend(gt->i915); in intel_gt_reset()
1239 gt_err(gt, "Failed to reset chip\n"); in intel_gt_reset()
1243 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) in intel_gt_reset()
1244 intel_irq_resume(gt->i915); in intel_gt_reset()
1246 intel_overlay_reset(gt->i915); in intel_gt_reset()
1248 /* sanitize uC after engine reset */ in intel_gt_reset()
1249 if (!intel_uc_uses_guc_submission(>->uc)) in intel_gt_reset()
1250 intel_uc_reset_prepare(>->uc); in intel_gt_reset()
1255 * Ring buffer needs to be re-initialized in the KMS case, or if X in intel_gt_reset()
1256 * was running at the time of the reset (i.e. we weren't VT in intel_gt_reset()
1261 gt_err(gt, "Failed to initialise HW following reset (%d)\n", ret); in intel_gt_reset()
1272 mutex_unlock(>->reset.mutex); in intel_gt_reset()
1277 * History tells us that if we cannot reset the GPU now, we in intel_gt_reset()
1279 * subsequently. On failing the reset, we mark the driver in intel_gt_reset()
1288 add_taint_for_CI(gt->i915, TAINT_WARN); in intel_gt_reset()
1295 * intel_gt_reset_all_engines() - Reset all engines in the given gt.
1296 * @gt: the GT to reset all engines for.
1309 * intel_gt_reset_engine() - Reset a specific engine within a gt.
1310 * @engine: engine to be reset.
1319 return __intel_gt_reset(engine->gt, engine->mask); in intel_gt_reset_engine()
1324 struct intel_gt *gt = engine->gt; in __intel_engine_reset_bh()
1327 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags); in __intel_engine_reset_bh()
1328 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)); in __intel_engine_reset_bh()
1331 return -ENODEV; in __intel_engine_reset_bh()
1339 drm_notice(&engine->i915->drm, in __intel_engine_reset_bh()
1340 "Resetting %s for %s\n", engine->name, msg); in __intel_engine_reset_bh()
1341 i915_increase_reset_engine_count(&engine->i915->gpu_error, engine); in __intel_engine_reset_bh()
1345 /* If we fail here, we expect to fallback to a global reset */ in __intel_engine_reset_bh()
1346 ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret); in __intel_engine_reset_bh()
1359 * have been reset to their default values. Follow the init_ring in __intel_engine_reset_bh()
1360 * process to program RING_MODE, HWSP and re-enable submission. in __intel_engine_reset_bh()
1372 * intel_engine_reset - reset GPU engine to recover from a hang
1373 * @engine: engine to reset
1374 * @msg: reason for GPU reset; or NULL for no drm_notice()
1376 * Reset a specific GPU engine. Useful if a hang is detected.
1377 * Returns zero on successful reset or otherwise an error code.
1380 * - identifies the request that caused the hang and it is dropped
1381 * - reset engine (which will force the engine to idle)
1382 * - re-init/configure engine
1399 struct kobject *kobj = >->i915->drm.primary->kdev->kobj; in intel_gt_reset_global()
1410 /* Use a watchdog to ensure that our reset completes */ in intel_gt_reset_global()
1412 intel_display_reset_prepare(gt->i915); in intel_gt_reset_global()
1416 intel_display_reset_finish(gt->i915); in intel_gt_reset_global()
1419 if (!test_bit(I915_WEDGED, >->reset.flags)) in intel_gt_reset_global()
1424 * intel_gt_handle_error - handle a gpu error
1426 * @engine_mask: mask representing engines that are hung
1460 * request that won't finish until the reset is done. This in intel_gt_handle_error()
1462 * simulated reset via debugfs, so get an RPM reference. in intel_gt_handle_error()
1464 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_gt_handle_error()
1466 engine_mask &= gt->info.engine_mask; in intel_gt_handle_error()
1474 * Try engine reset when available. We fall back to full reset if in intel_gt_handle_error()
1475 * single reset fails. in intel_gt_handle_error()
1477 if (!intel_uc_uses_guc_submission(>->uc) && in intel_gt_handle_error()
1482 if (test_and_set_bit(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1483 >->reset.flags)) in intel_gt_handle_error()
1487 engine_mask &= ~engine->mask; in intel_gt_handle_error()
1489 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1490 >->reset.flags); in intel_gt_handle_error()
1498 /* Full reset needs the mutex, stop any other user trying to do so. */ in intel_gt_handle_error()
1499 if (test_and_set_bit(I915_RESET_BACKOFF, >->reset.flags)) { in intel_gt_handle_error()
1500 wait_event(gt->reset.queue, in intel_gt_handle_error()
1501 !test_bit(I915_RESET_BACKOFF, >->reset.flags)); in intel_gt_handle_error()
1502 goto out; /* piggy-back on the other reset */ in intel_gt_handle_error()
1509 * Prevent any other reset-engine attempt. We don't do this for GuC in intel_gt_handle_error()
1510 * submission the GuC owns the per-engine reset, not the i915. in intel_gt_handle_error()
1512 if (!intel_uc_uses_guc_submission(>->uc)) { in intel_gt_handle_error()
1514 while (test_and_set_bit(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1515 >->reset.flags)) in intel_gt_handle_error()
1516 wait_on_bit(>->reset.flags, in intel_gt_handle_error()
1517 I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1523 synchronize_srcu_expedited(>->reset.backoff_srcu); in intel_gt_handle_error()
1527 if (!intel_uc_uses_guc_submission(>->uc)) { in intel_gt_handle_error()
1529 clear_bit_unlock(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1530 >->reset.flags); in intel_gt_handle_error()
1532 clear_bit_unlock(I915_RESET_BACKOFF, >->reset.flags); in intel_gt_handle_error()
1534 wake_up_all(>->reset.queue); in intel_gt_handle_error()
1537 intel_runtime_pm_put(gt->uncore->rpm, wakeref); in intel_gt_handle_error()
1542 might_lock(>->reset.backoff_srcu); in _intel_gt_reset_lock()
1547 while (test_bit(I915_RESET_BACKOFF, >->reset.flags)) { in _intel_gt_reset_lock()
1551 return -EBUSY; in _intel_gt_reset_lock()
1553 if (wait_event_interruptible(gt->reset.queue, in _intel_gt_reset_lock()
1555 >->reset.flags))) in _intel_gt_reset_lock()
1556 return -EINTR; in _intel_gt_reset_lock()
1560 *srcu = srcu_read_lock(>->reset.backoff_srcu); in _intel_gt_reset_lock()
1577 __releases(>->reset.backoff_srcu) in intel_gt_reset_unlock()
1579 srcu_read_unlock(>->reset.backoff_srcu, tag); in intel_gt_reset_unlock()
1590 return -EIO; in intel_gt_terminally_wedged()
1592 /* Reset still in progress? Maybe we will recover? */ in intel_gt_terminally_wedged()
1593 if (wait_event_interruptible(gt->reset.queue, in intel_gt_terminally_wedged()
1595 >->reset.flags))) in intel_gt_terminally_wedged()
1596 return -EINTR; in intel_gt_terminally_wedged()
1598 return intel_gt_is_wedged(gt) ? -EIO : 0; in intel_gt_terminally_wedged()
1606 i915_disable_error_state(gt->i915, -ENODEV); in intel_gt_set_wedged_on_init()
1607 set_bit(I915_WEDGED_ON_INIT, >->reset.flags); in intel_gt_set_wedged_on_init()
1609 /* Wedged on init is non-recoverable */ in intel_gt_set_wedged_on_init()
1610 add_taint_for_CI(gt->i915, TAINT_WARN); in intel_gt_set_wedged_on_init()
1616 i915_disable_error_state(gt->i915, -ENODEV); in intel_gt_set_wedged_on_fini()
1617 set_bit(I915_WEDGED_ON_FINI, >->reset.flags); in intel_gt_set_wedged_on_fini()
1623 init_waitqueue_head(>->reset.queue); in intel_gt_init_reset()
1624 mutex_init(>->reset.mutex); in intel_gt_init_reset()
1625 init_srcu_struct(>->reset.backoff_srcu); in intel_gt_init_reset()
1626 INIT_WORK(>->wedge, set_wedged_work); in intel_gt_init_reset()
1632 * by forcing the reset. Therefore during the reset we must not in intel_gt_init_reset()
1633 * re-enter the shrinker. By declaring that we take the reset mutex in intel_gt_init_reset()
1635 * fs-reclaim or taking related locks during reset. in intel_gt_init_reset()
1637 i915_gem_shrinker_taints_mutex(gt->i915, >->reset.mutex); in intel_gt_init_reset()
1640 __set_bit(I915_WEDGED, >->reset.flags); in intel_gt_init_reset()
1645 cleanup_srcu_struct(>->reset.backoff_srcu); in intel_gt_fini_reset()
1652 gt_err(w->gt, "%s timed out, cancelling all in-flight rendering.\n", w->name); in intel_wedge_me()
1653 set_wedged_work(&w->gt->wedge); in intel_wedge_me()
1661 w->gt = gt; in __intel_init_wedge()
1662 w->name = name; in __intel_init_wedge()
1664 INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me); in __intel_init_wedge()
1665 queue_delayed_work(gt->i915->unordered_wq, &w->work, timeout); in __intel_init_wedge()
1670 cancel_delayed_work_sync(&w->work); in __intel_fini_wedge()
1671 destroy_delayed_work_on_stack(&w->work); in __intel_fini_wedge()
1672 w->gt = NULL; in __intel_fini_wedge()
1677 * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
1681 if (GRAPHICS_VER(gt->i915) < 11) in intel_engine_reset_needs_wa_22011802037()
1687 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_engine_reset_needs_wa_22011802037()