40  * right after the commands taking care of alignment so we should sufficient
50 static int render_state_setup(struct intel_renderstate *so,  in render_state_setup()  argument
53 	const struct intel_renderstate_rodata *rodata = so->rodata;  in render_state_setup()
58 	d = i915_gem_object_pin_map(so->vma->obj, I915_MAP_WB);  in render_state_setup()
66 			u64 r = s + i915_vma_offset(so->vma);  in render_state_setup()
89 	so->batch_offset = i915_ggtt_offset(so->vma);  in render_state_setup()
90 	so->batch_size = rodata->batch_items * sizeof(u32);  in render_state_setup()
95 	so->aux_offset = i * sizeof(u32);  in render_state_setup()
125 	so->aux_size = i * sizeof(u32) - so->aux_offset;  in render_state_setup()
126 	so->aux_offset += so->batch_offset;  in render_state_setup()
131 	so->aux_size = ALIGN(so->aux_size, 8);  in render_state_setup()
135 	__i915_gem_object_flush_map(so->vma->obj, 0, i * sizeof(u32));  in render_state_setup()
136 	__i915_gem_object_release_map(so->vma->obj);  in render_state_setup()
142 int intel_renderstate_init(struct intel_renderstate *so,  in intel_renderstate_init()  argument
149 	memset(so, 0, sizeof(*so));  in intel_renderstate_init()
151 	so->rodata = render_state_get_rodata(engine);  in intel_renderstate_init()
152 	if (so->rodata) {  in intel_renderstate_init()
153 		if (so->rodata->batch_items * 4 > PAGE_SIZE)  in intel_renderstate_init()
160 		so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);  in intel_renderstate_init()
161 		if (IS_ERR(so->vma)) {  in intel_renderstate_init()
162 			err = PTR_ERR(so->vma);  in intel_renderstate_init()
167 	i915_gem_ww_ctx_init(&so->ww, true);  in intel_renderstate_init()
169 	err = intel_context_pin_ww(ce, &so->ww);  in intel_renderstate_init()
174 	if (!err && !so->rodata)  in intel_renderstate_init()
177 	err = i915_gem_object_lock(so->vma->obj, &so->ww);  in intel_renderstate_init()
181 	err = i915_vma_pin_ww(so->vma, &so->ww, 0, 0, PIN_GLOBAL | PIN_HIGH);  in intel_renderstate_init()
185 	err = render_state_setup(so, engine->i915);  in intel_renderstate_init()
192 	i915_vma_unpin(so->vma);  in intel_renderstate_init()
197 		err = i915_gem_ww_ctx_backoff(&so->ww);  in intel_renderstate_init()
201 	i915_gem_ww_ctx_fini(&so->ww);  in intel_renderstate_init()
205 	so->vma = NULL;  in intel_renderstate_init()
209 int intel_renderstate_emit(struct intel_renderstate *so,  in intel_renderstate_emit()  argument
215 	if (!so->vma)  in intel_renderstate_emit()
218 	err = i915_vma_move_to_active(so->vma, rq, 0);  in intel_renderstate_emit()
223 				    so->batch_offset, so->batch_size,  in intel_renderstate_emit()
228 	if (so->aux_size > 8) {  in intel_renderstate_emit()
230 					    so->aux_offset, so->aux_size,  in intel_renderstate_emit()
239 void intel_renderstate_fini(struct intel_renderstate *so,  in intel_renderstate_fini()  argument
242 	if (so->vma) {  in intel_renderstate_fini()
243 		i915_vma_unpin(so->vma);  in intel_renderstate_fini()
244 		i915_vma_close(so->vma);  in intel_renderstate_fini()
248 	i915_gem_ww_ctx_fini(&so->ww);  in intel_renderstate_fini()
250 	if (so->vma)  in intel_renderstate_fini()
251 		i915_gem_object_put(so->vma->obj);  in intel_renderstate_fini()