Lines Matching full:gt
13 * DOC: GT Multicast/Replicated (MCR) Register Support
15 * Some GT registers are designed as "multicast" or "replicated" registers:
108 void intel_gt_mcr_init(struct intel_gt *gt) in intel_gt_mcr_init() argument
110 struct drm_i915_private *i915 = gt->i915; in intel_gt_mcr_init()
114 spin_lock_init(>->mcr_lock); in intel_gt_mcr_init()
121 gt->info.mslice_mask = in intel_gt_mcr_init()
122 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, in intel_gt_mcr_init()
124 gt->info.mslice_mask |= in intel_gt_mcr_init()
125 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
128 if (!gt->info.mslice_mask) /* should be impossible! */ in intel_gt_mcr_init()
129 gt_warn(gt, "mslice mask all zero!\n"); in intel_gt_mcr_init()
132 if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) { in intel_gt_mcr_init()
133 gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table; in intel_gt_mcr_init()
136 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in intel_gt_mcr_init()
137 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) in intel_gt_mcr_init()
139 intel_uncore_read(gt->uncore, in intel_gt_mcr_init()
143 intel_uncore_read(gt->uncore, XEHP_FUSE4)); in intel_gt_mcr_init()
150 gt->info.l3bank_mask |= 0x3 << 2 * i; in intel_gt_mcr_init()
152 gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table; in intel_gt_mcr_init()
153 gt->steering_table[L3BANK] = xelpg_l3bank_steering_table; in intel_gt_mcr_init()
154 gt->steering_table[DSS] = xelpg_dss_steering_table; in intel_gt_mcr_init()
156 gt->steering_table[MSLICE] = dg2_mslice_steering_table; in intel_gt_mcr_init()
157 gt->steering_table[LNCF] = dg2_lncf_steering_table; in intel_gt_mcr_init()
165 gt->steering_table[L3BANK] = icl_l3bank_steering_table; in intel_gt_mcr_init()
166 gt->info.l3bank_mask = in intel_gt_mcr_init()
167 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
169 if (!gt->info.l3bank_mask) /* should be impossible! */ in intel_gt_mcr_init()
170 gt_warn(gt, "L3 bank mask is all zero!\n"); in intel_gt_mcr_init()
195 * @gt: GT to read register from
207 static u32 rw_with_mcr_steering_fw(struct intel_gt *gt, in rw_with_mcr_steering_fw() argument
211 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering_fw()
214 lockdep_assert_held(>->mcr_lock); in rw_with_mcr_steering_fw()
284 static u32 rw_with_mcr_steering(struct intel_gt *gt, in rw_with_mcr_steering() argument
289 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering()
300 intel_gt_mcr_lock(gt, &flags); in rw_with_mcr_steering()
304 val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value); in rw_with_mcr_steering()
308 intel_gt_mcr_unlock(gt, flags); in rw_with_mcr_steering()
315 * @gt: GT structure
323 * Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this
327 void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags) in intel_gt_mcr_lock() argument
328 __acquires(>->mcr_lock) in intel_gt_mcr_lock()
333 lockdep_assert_not_held(>->uncore->lock); in intel_gt_mcr_lock()
340 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_lock()
346 * accessed. Grabbing GT forcewake and holding it over the in intel_gt_mcr_lock()
354 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT); in intel_gt_mcr_lock()
356 err = wait_for(intel_uncore_read_fw(gt->uncore, in intel_gt_mcr_lock()
366 spin_lock_irqsave(>->mcr_lock, __flags); in intel_gt_mcr_lock()
376 gt_err_ratelimited(gt, "hardware MCR steering semaphore timed out"); in intel_gt_mcr_lock()
377 add_taint_for_CI(gt->i915, TAINT_WARN); /* CI is now unreliable */ in intel_gt_mcr_lock()
383 * @gt: GT structure
388 * Context: Releases gt->mcr_lock
390 void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags) in intel_gt_mcr_unlock() argument
391 __releases(>->mcr_lock) in intel_gt_mcr_unlock()
393 spin_unlock_irqrestore(>->mcr_lock, flags); in intel_gt_mcr_unlock()
395 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_unlock()
396 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); in intel_gt_mcr_unlock()
398 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT); in intel_gt_mcr_unlock()
404 * @gt: GT structure
412 void intel_gt_mcr_lock_sanitize(struct intel_gt *gt) in intel_gt_mcr_lock_sanitize() argument
418 lockdep_assert_not_held(>->mcr_lock); in intel_gt_mcr_lock_sanitize()
420 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_lock_sanitize()
421 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); in intel_gt_mcr_lock_sanitize()
426 * @gt: GT structure
431 * Context: Takes and releases gt->mcr_lock
436 u32 intel_gt_mcr_read(struct intel_gt *gt, in intel_gt_mcr_read() argument
440 return rw_with_mcr_steering(gt, reg, FW_REG_READ, group, instance, 0); in intel_gt_mcr_read()
445 * @gt: GT structure
454 * Context: Calls a function that takes and releases gt->mcr_lock
456 void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, in intel_gt_mcr_unicast_write() argument
459 rw_with_mcr_steering(gt, reg, FW_REG_WRITE, group, instance, value); in intel_gt_mcr_unicast_write()
464 * @gt: GT structure
470 * Context: Takes and releases gt->mcr_lock
472 void intel_gt_mcr_multicast_write(struct intel_gt *gt, in intel_gt_mcr_multicast_write() argument
477 intel_gt_mcr_lock(gt, &flags); in intel_gt_mcr_multicast_write()
483 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write()
484 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); in intel_gt_mcr_multicast_write()
486 intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value); in intel_gt_mcr_multicast_write()
488 intel_gt_mcr_unlock(gt, flags); in intel_gt_mcr_multicast_write()
493 * @gt: GT structure
502 * Context: The caller must hold gt->mcr_lock.
504 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value) in intel_gt_mcr_multicast_write_fw() argument
506 lockdep_assert_held(>->mcr_lock); in intel_gt_mcr_multicast_write_fw()
512 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write_fw()
513 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); in intel_gt_mcr_multicast_write_fw()
515 intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value); in intel_gt_mcr_multicast_write_fw()
520 * @gt: GT structure
534 * Context: Calls functions that take and release gt->mcr_lock
538 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, in intel_gt_mcr_multicast_rmw() argument
541 u32 val = intel_gt_mcr_read_any(gt, reg); in intel_gt_mcr_multicast_rmw()
543 intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set); in intel_gt_mcr_multicast_rmw()
551 * @gt: GT structure
562 static bool reg_needs_read_steering(struct intel_gt *gt, in reg_needs_read_steering() argument
569 if (likely(!gt->steering_table[type])) in reg_needs_read_steering()
573 offset += gt->uncore->gsi_offset; in reg_needs_read_steering()
575 for (entry = gt->steering_table[type]; entry->end; entry++) { in reg_needs_read_steering()
585 * @gt: GT structure
593 static void get_nonterminated_steering(struct intel_gt *gt, in get_nonterminated_steering() argument
602 *instance = __ffs(gt->info.l3bank_mask); in get_nonterminated_steering()
605 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); in get_nonterminated_steering()
606 *group = __ffs(gt->info.mslice_mask); in get_nonterminated_steering()
614 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); in get_nonterminated_steering()
615 *group = __ffs(gt->info.mslice_mask) << 1; in get_nonterminated_steering()
619 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
623 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); in get_nonterminated_steering()
636 if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0)) in get_nonterminated_steering()
652 * @gt: GT structure
662 void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, in intel_gt_mcr_get_nonterminated_steering() argument
669 if (reg_needs_read_steering(gt, reg, type)) { in intel_gt_mcr_get_nonterminated_steering()
670 get_nonterminated_steering(gt, type, group, instance); in intel_gt_mcr_get_nonterminated_steering()
675 *group = gt->default_steering.groupid; in intel_gt_mcr_get_nonterminated_steering()
676 *instance = gt->default_steering.instanceid; in intel_gt_mcr_get_nonterminated_steering()
681 * @gt: GT structure
684 * Reads a GT MCR register. The read will be steered to a non-terminated
690 * Context: The caller must hold gt->mcr_lock.
694 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg) in intel_gt_mcr_read_any_fw() argument
699 lockdep_assert_held(>->mcr_lock); in intel_gt_mcr_read_any_fw()
702 if (reg_needs_read_steering(gt, reg, type)) { in intel_gt_mcr_read_any_fw()
703 get_nonterminated_steering(gt, type, &group, &instance); in intel_gt_mcr_read_any_fw()
704 return rw_with_mcr_steering_fw(gt, reg, in intel_gt_mcr_read_any_fw()
710 return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any_fw()
715 * @gt: GT structure
718 * Reads a GT MCR register. The read will be steered to a non-terminated
721 * Context: Calls a function that takes and releases gt->mcr_lock.
725 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg) in intel_gt_mcr_read_any() argument
731 if (reg_needs_read_steering(gt, reg, type)) { in intel_gt_mcr_read_any()
732 get_nonterminated_steering(gt, type, &group, &instance); in intel_gt_mcr_read_any()
733 return rw_with_mcr_steering(gt, reg, in intel_gt_mcr_read_any()
739 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any()
743 struct intel_gt *gt, in report_steering_type() argument
752 if (!gt->steering_table[type]) { in report_steering_type()
758 get_nonterminated_steering(gt, type, &group, &instance); in report_steering_type()
765 for (entry = gt->steering_table[type]; entry->end; entry++) in report_steering_type()
769 void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, in intel_gt_mcr_report_steering() argument
776 if (GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)) in intel_gt_mcr_report_steering()
778 gt->default_steering.groupid, in intel_gt_mcr_report_steering()
779 gt->default_steering.instanceid); in intel_gt_mcr_report_steering()
781 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_report_steering()
783 if (gt->steering_table[i]) in intel_gt_mcr_report_steering()
784 report_steering_type(p, gt, i, dump_table); in intel_gt_mcr_report_steering()
785 } else if (HAS_MSLICE_STEERING(gt->i915)) { in intel_gt_mcr_report_steering()
786 report_steering_type(p, gt, MSLICE, dump_table); in intel_gt_mcr_report_steering()
787 report_steering_type(p, gt, LNCF, dump_table); in intel_gt_mcr_report_steering()
793 * @gt: GT structure
801 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, in intel_gt_mcr_get_ss_steering() argument
804 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) { in intel_gt_mcr_get_ss_steering()
816 * @gt: GT structure
826 * (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value
841 * Context: Calls a function that takes and releases gt->mcr_lock
844 int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, in intel_gt_mcr_wait_for_reg() argument
853 lockdep_assert_not_held(>->mcr_lock); in intel_gt_mcr_wait_for_reg()
855 #define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value) in intel_gt_mcr_wait_for_reg()