31 gen11_gt_engine_identity(struct intel_gt *gt,  in gen11_gt_engine_identity()  argument
34 	void __iomem * const regs = intel_uncore_regs(gt->uncore);  in gen11_gt_engine_identity()
38 	lockdep_assert_held(gt->irq_lock);  in gen11_gt_engine_identity()
53 		gt_err(gt, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",  in gen11_gt_engine_identity()
65 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,  in gen11_other_irq_handler()  argument
68 	struct intel_gt *media_gt = gt->i915->media_gt;  in gen11_other_irq_handler()
71 		return guc_irq_handler(gt_to_guc(gt), iir);  in gen11_other_irq_handler()
76 		return gen11_rps_irq_handler(&gt->rps, iir);  in gen11_other_irq_handler()
81 		return intel_pxp_irq_handler(gt->i915->pxp, iir);  in gen11_other_irq_handler()
84 		return intel_gsc_irq_handler(gt, iir);  in gen11_other_irq_handler()
87 		return intel_gsc_proxy_irq_handler(&gt->uc.gsc, iir);  in gen11_other_irq_handler()
93 static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)  in pick_gt()  argument
95 	struct intel_gt *media_gt = gt->i915->media_gt;  in pick_gt()
97 	/* we expect the non-media gt to be passed in */  in pick_gt()
98 	GEM_BUG_ON(gt == media_gt);  in pick_gt()
101 		return gt;  in pick_gt()
115 		return gt;  in pick_gt()
120 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)  in gen11_gt_identity_handler()  argument
131 	 * another GT.  in gen11_gt_identity_handler()
133 	gt = pick_gt(gt, class, instance);  in gen11_gt_identity_handler()
136 		struct intel_engine_cs *engine = gt->engine_class[class][instance];  in gen11_gt_identity_handler()
142 		return gen11_other_irq_handler(gt, instance, intr);  in gen11_gt_identity_handler()
149 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)  in gen11_gt_bank_handler()  argument
151 	void __iomem * const regs = intel_uncore_regs(gt->uncore);  in gen11_gt_bank_handler()
155 	lockdep_assert_held(gt->irq_lock);  in gen11_gt_bank_handler()
160 		const u32 ident = gen11_gt_engine_identity(gt, bank, bit);  in gen11_gt_bank_handler()
162 		gen11_gt_identity_handler(gt, ident);  in gen11_gt_bank_handler()
169 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)  in gen11_gt_irq_handler()  argument
173 	spin_lock(gt->irq_lock);  in gen11_gt_irq_handler()
177 			gen11_gt_bank_handler(gt, bank);  in gen11_gt_irq_handler()
180 	spin_unlock(gt->irq_lock);  in gen11_gt_irq_handler()
183 bool gen11_gt_reset_one_iir(struct intel_gt *gt,  in gen11_gt_reset_one_iir()  argument
186 	void __iomem * const regs = intel_uncore_regs(gt->uncore);  in gen11_gt_reset_one_iir()
189 	lockdep_assert_held(gt->irq_lock);  in gen11_gt_reset_one_iir()
197 		gen11_gt_engine_identity(gt, bank, bit);  in gen11_gt_reset_one_iir()
200 		 * We locked GT INT DW by reading it. If we want to (try  in gen11_gt_reset_one_iir()
213 void gen11_gt_irq_reset(struct intel_gt *gt)  in gen11_gt_irq_reset()  argument
215 	struct intel_uncore *uncore = gt->uncore;  in gen11_gt_irq_reset()
220 	if (CCS_MASK(gt))  in gen11_gt_irq_reset()
222 	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))  in gen11_gt_irq_reset()
228 	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))  in gen11_gt_irq_reset()
230 	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))  in gen11_gt_irq_reset()
232 	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))  in gen11_gt_irq_reset()
234 	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))  in gen11_gt_irq_reset()
238 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))  in gen11_gt_irq_reset()
240 	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))  in gen11_gt_irq_reset()
243 	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))  in gen11_gt_irq_reset()
245 	if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))  in gen11_gt_irq_reset()
247 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))  in gen11_gt_irq_reset()
249 	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))  in gen11_gt_irq_reset()
261 void gen11_gt_irq_postinstall(struct intel_gt *gt)  in gen11_gt_irq_postinstall()  argument
263 	struct intel_uncore *uncore = gt->uncore;  in gen11_gt_irq_postinstall()
265 	u32 guc_mask = intel_uc_wants_guc(&gt->uc) ? GUC_INTR_GUC2HOST : 0;  in gen11_gt_irq_postinstall()
271 	if (!intel_uc_wants_guc_submission(&gt->uc))  in gen11_gt_irq_postinstall()
279 	if (HAS_ENGINE(gt, GSC0)) {  in gen11_gt_irq_postinstall()
286 	} else if (HAS_HECI_GSC(gt->i915)) {  in gen11_gt_irq_postinstall()
295 	if (CCS_MASK(gt))  in gen11_gt_irq_postinstall()
303 	if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))  in gen11_gt_irq_postinstall()
305 	if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))  in gen11_gt_irq_postinstall()
307 	if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))  in gen11_gt_irq_postinstall()
309 	if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))  in gen11_gt_irq_postinstall()
313 	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))  in gen11_gt_irq_postinstall()
315 	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))  in gen11_gt_irq_postinstall()
318 	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))  in gen11_gt_irq_postinstall()
320 	if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))  in gen11_gt_irq_postinstall()
322 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))  in gen11_gt_irq_postinstall()
332 		u32 mask = gt->type == GT_MEDIA ?  in gen11_gt_irq_postinstall()
339 		/* we might not be the first GT to write this reg */  in gen11_gt_irq_postinstall()
347 	gt->pm_ier = 0x0;  in gen11_gt_irq_postinstall()
348 	gt->pm_imr = ~gt->pm_ier;  in gen11_gt_irq_postinstall()
353 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)  in gen5_gt_irq_handler()  argument
356 		intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],  in gen5_gt_irq_handler()
360 		intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],  in gen5_gt_irq_handler()
364 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir)  in gen7_parity_error_irq_handler()  argument
366 	if (!HAS_L3_DPF(gt->i915))  in gen7_parity_error_irq_handler()
369 	spin_lock(gt->irq_lock);  in gen7_parity_error_irq_handler()
370 	gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915));  in gen7_parity_error_irq_handler()
371 	spin_unlock(gt->irq_lock);  in gen7_parity_error_irq_handler()
374 		gt->i915->l3_parity.which_slice |= 1 << 1;  in gen7_parity_error_irq_handler()
377 		gt->i915->l3_parity.which_slice |= 1 << 0;  in gen7_parity_error_irq_handler()
379 	queue_work(gt->i915->unordered_wq, &gt->i915->l3_parity.error_work);  in gen7_parity_error_irq_handler()
382 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)  in gen6_gt_irq_handler()  argument
385 		intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],  in gen6_gt_irq_handler()
389 		intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],  in gen6_gt_irq_handler()
393 		intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],  in gen6_gt_irq_handler()
399 		gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir);  in gen6_gt_irq_handler()
401 	if (gt_iir & GT_PARITY_ERROR(gt->i915))  in gen6_gt_irq_handler()
402 		gen7_parity_error_irq_handler(gt, gt_iir);  in gen6_gt_irq_handler()
405 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)  in gen8_gt_irq_handler()  argument
407 	void __iomem * const regs = intel_uncore_regs(gt->uncore);  in gen8_gt_irq_handler()
413 			intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0],  in gen8_gt_irq_handler()
415 			intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0],  in gen8_gt_irq_handler()
424 			intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0],  in gen8_gt_irq_handler()
426 			intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1],  in gen8_gt_irq_handler()
435 			intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],  in gen8_gt_irq_handler()
444 			gen6_rps_irq_handler(&gt->rps, iir);  in gen8_gt_irq_handler()
445 			guc_irq_handler(gt_to_guc(gt), iir >> 16);  in gen8_gt_irq_handler()
451 void gen8_gt_irq_reset(struct intel_gt *gt)  in gen8_gt_irq_reset()  argument
453 	struct intel_uncore *uncore = gt->uncore;  in gen8_gt_irq_reset()
455 	GEN8_IRQ_RESET_NDX(uncore, GT, 0);  in gen8_gt_irq_reset()
456 	GEN8_IRQ_RESET_NDX(uncore, GT, 1);  in gen8_gt_irq_reset()
457 	GEN8_IRQ_RESET_NDX(uncore, GT, 2);  in gen8_gt_irq_reset()
458 	GEN8_IRQ_RESET_NDX(uncore, GT, 3);  in gen8_gt_irq_reset()
461 void gen8_gt_irq_postinstall(struct intel_gt *gt)  in gen8_gt_irq_postinstall()  argument
475 	struct intel_uncore *uncore = gt->uncore;  in gen8_gt_irq_postinstall()
477 	gt->pm_ier = 0x0;  in gen8_gt_irq_postinstall()
478 	gt->pm_imr = ~gt->pm_ier;  in gen8_gt_irq_postinstall()
479 	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);  in gen8_gt_irq_postinstall()
480 	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);  in gen8_gt_irq_postinstall()
485 	GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);  in gen8_gt_irq_postinstall()
486 	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);  in gen8_gt_irq_postinstall()
489 static void gen5_gt_update_irq(struct intel_gt *gt,  in gen5_gt_update_irq()  argument
493 	lockdep_assert_held(gt->irq_lock);  in gen5_gt_update_irq()
497 	gt->gt_imr &= ~interrupt_mask;  in gen5_gt_update_irq()
498 	gt->gt_imr |= (~enabled_irq_mask & interrupt_mask);  in gen5_gt_update_irq()
499 	intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr);  in gen5_gt_update_irq()
502 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask)  in gen5_gt_enable_irq()  argument
504 	gen5_gt_update_irq(gt, mask, mask);  in gen5_gt_enable_irq()
505 	intel_uncore_posting_read_fw(gt->uncore, GTIMR);  in gen5_gt_enable_irq()
508 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask)  in gen5_gt_disable_irq()  argument
510 	gen5_gt_update_irq(gt, mask, 0);  in gen5_gt_disable_irq()
513 void gen5_gt_irq_reset(struct intel_gt *gt)  in gen5_gt_irq_reset()  argument
515 	struct intel_uncore *uncore = gt->uncore;  in gen5_gt_irq_reset()
517 	GEN3_IRQ_RESET(uncore, GT);  in gen5_gt_irq_reset()
518 	if (GRAPHICS_VER(gt->i915) >= 6)  in gen5_gt_irq_reset()
522 void gen5_gt_irq_postinstall(struct intel_gt *gt)  in gen5_gt_irq_postinstall()  argument
524 	struct intel_uncore *uncore = gt->uncore;  in gen5_gt_irq_postinstall()
528 	gt->gt_imr = ~0;  in gen5_gt_irq_postinstall()
529 	if (HAS_L3_DPF(gt->i915)) {  in gen5_gt_irq_postinstall()
531 		gt->gt_imr = ~GT_PARITY_ERROR(gt->i915);  in gen5_gt_irq_postinstall()
532 		gt_irqs |= GT_PARITY_ERROR(gt->i915);  in gen5_gt_irq_postinstall()
536 	if (GRAPHICS_VER(gt->i915) == 5)  in gen5_gt_irq_postinstall()
541 	GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);  in gen5_gt_irq_postinstall()
543 	if (GRAPHICS_VER(gt->i915) >= 6) {  in gen5_gt_irq_postinstall()
548 		if (HAS_ENGINE(gt, VECS0)) {  in gen5_gt_irq_postinstall()
550 			gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;  in gen5_gt_irq_postinstall()
553 		gt->pm_imr = 0xffffffff;  in gen5_gt_irq_postinstall()
554 		GEN3_IRQ_INIT(uncore, GEN6_PM, gt->pm_imr, pm_irqs);  in gen5_gt_irq_postinstall()