Lines Matching +full:hardware +full:- +full:bound
1 /* SPDX-License-Identifier: MIT */
23 ((gt)->type != GT_MEDIA && \
24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
25 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
37 ((gt) && (gt)->type == GT_MEDIA && \
38 MEDIA_VER_FULL((gt)->i915) >= (from) && \
39 MEDIA_VER_FULL((gt)->i915) <= (until)))
43 * a stepping in the range [from, until). The lower stepping bound is
44 * inclusive, the upper bound is exclusive. The most common use-case of this
46 * ("from") at which the hardware issue is first present and another stepping
47 * ("until") at which a hardware fix is present and the software workaround is
54 * stepping bound for the specified IP version.
59 IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
63 * a stepping in the range [from, until). The lower stepping bound is
64 * inclusive, the upper bound is exclusive. The most common use-case of this
66 * ("from") at which the hardware issue is first present and another stepping
67 * ("until") at which a hardware fix is present and the software workaround is
69 * workarounds that have no upper stepping bound for the specified IP version.
77 IS_MEDIA_STEP((gt)->i915, (from), (until))))
81 GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
87 return !gt->info.id; in gt_is_root()
94 intel_gt_needs_wa_16018031267(engine->gt) && \
95 engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
124 return guc_to_gt(guc)->i915; in guc_to_i915()
129 return >->uc.guc; in gt_to_guc()
158 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
163 return test_bit(I915_WEDGED_ON_INIT, >->reset.flags) || in intel_gt_has_unrecoverable_error()
164 test_bit(I915_WEDGED_ON_FINI, >->reset.flags); in intel_gt_has_unrecoverable_error()
170 !test_bit(I915_WEDGED, >->reset.flags)); in intel_gt_is_wedged()
172 return unlikely(test_bit(I915_WEDGED, >->reset.flags)); in intel_gt_is_wedged()
182 for_each_if(((gt__) = (i915__)->gt[(id__)]))
189 for_each_if ((engine__) = (gt__)->engine[(id__)])
193 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
195 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
213 queue_work(system_highpri_wq, >->wedge); in intel_gt_set_wedged_async()