Lines Matching +full:mipi +full:- +full:dpi
88 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty()
96 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
108 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
124 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
133 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; in intel_dsi_host_transfer()
134 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer()
135 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
148 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
164 drm_err(display->drm, in intel_dsi_host_transfer()
171 if (msg->rx_len) { in intel_dsi_host_transfer()
178 drm_err(display->drm, in intel_dsi_host_transfer()
185 /* ->rx_len is set only for reads */ in intel_dsi_host_transfer()
186 if (msg->rx_len) { in intel_dsi_host_transfer()
190 drm_err(display->drm, in intel_dsi_host_transfer()
193 read_data(display, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
226 struct intel_display *display = to_intel_display(&intel_dsi->base); in dpi_send_cmd()
240 drm_dbg_kms(display->drm, in dpi_send_cmd()
247 drm_err(display->drm, in dpi_send_cmd()
271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config()
273 struct intel_connector *intel_connector = intel_dsi->attached_connector; in intel_dsi_compute_config()
274 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
277 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
278 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
279 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
289 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dsi_compute_config()
290 return -EINVAL; in intel_dsi_compute_config()
293 adjusted_mode->flags = 0; in intel_dsi_compute_config()
295 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in intel_dsi_compute_config()
296 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
298 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
302 pipe_config->mode_flags |= in intel_dsi_compute_config()
306 if (intel_dsi->ports == BIT(PORT_C)) in intel_dsi_compute_config()
307 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
309 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
313 return -EINVAL; in intel_dsi_compute_config()
317 return -EINVAL; in intel_dsi_compute_config()
320 pipe_config->clock_set = true; in intel_dsi_compute_config()
332 /* Set the MIPI mode in glk_dsi_enable_io()
334 * Power ON MIPI IO first and then write into IO reset and LP wake bits in glk_dsi_enable_io()
336 for_each_dsi_port(port, intel_dsi->ports) in glk_dsi_enable_io()
343 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
351 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
354 drm_err(display->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
358 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
372 /* Wait for MIPI PHY status bit to set */ in glk_dsi_device_ready()
373 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
376 drm_err(display->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
383 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
396 drm_err(display->drm, "ULPS not active\n"); in glk_dsi_device_ready()
412 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
415 drm_err(display->drm, in glk_dsi_device_ready()
420 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
423 drm_err(display->drm, in glk_dsi_device_ready()
424 "D-PHY not entering LP-11 state\n"); in glk_dsi_device_ready()
435 drm_dbg_kms(display->drm, "\n"); in bxt_dsi_device_ready()
437 /* Enable MIPI PHY transparent latch */ in bxt_dsi_device_ready()
438 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
444 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
457 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready()
461 drm_dbg_kms(display->drm, "\n"); in vlv_dsi_device_ready()
472 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_device_ready()
478 /* Enable MIPI PHY transparent latch in vlv_dsi_device_ready()
479 * Common bit for both MIPI Port A & MIPI Port C in vlv_dsi_device_ready()
480 * No similar bit in MIPI Port C reg in vlv_dsi_device_ready()
497 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready()
514 for_each_dsi_port(port, intel_dsi->ports) in glk_dsi_enter_low_power_mode()
518 /* Wait for MIPI PHY status bit to unset */ in glk_dsi_enter_low_power_mode()
519 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
522 drm_err(display->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
526 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
529 drm_err(display->drm, in glk_dsi_enter_low_power_mode()
530 "MIPI IO Port is not powergated\n"); in glk_dsi_enter_low_power_mode()
543 /* Wait for MIPI PHY status bit to unset */ in glk_dsi_disable_mipi_io()
544 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
547 drm_err(display->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
550 /* Clear MIPI mode */ in glk_dsi_disable_mipi_io()
551 for_each_dsi_port(port, intel_dsi->ports) in glk_dsi_disable_mipi_io()
570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready()
574 drm_dbg_kms(display->drm, "\n"); in vlv_dsi_clear_device_ready()
575 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_clear_device_ready()
576 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ in vlv_dsi_clear_device_ready()
593 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI in vlv_dsi_clear_device_ready()
594 * Port A only. MIPI Port C has no similar bit for checking. in vlv_dsi_clear_device_ready()
599 drm_err(display->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
601 /* Disable MIPI PHY transparent latch */ in vlv_dsi_clear_device_ready()
614 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable()
615 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsi_port_enable()
619 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in intel_dsi_port_enable()
620 u32 temp = intel_dsi->pixel_overlap; in intel_dsi_port_enable()
623 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_port_enable()
634 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
643 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
644 temp |= (intel_dsi->dual_link - 1) in intel_dsi_port_enable()
649 temp |= crtc->pipe ? in intel_dsi_port_enable()
654 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) in intel_dsi_port_enable()
666 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_disable()
670 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_disable()
673 /* de-assert ip_tg_enable signal */ in intel_dsi_port_disable()
690 * Steps starting with MIPI refer to VBT sequences, note that for v2
695 * - power on - MIPIPanelPowerOn - power on
696 * - wait t1+t2 - wait t1+t2
697 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
698 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
699 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
700 * - MIPITearOn
701 * - MIPIDisplayOn
702 * - turn on DPI - turn on DPI - set pipe to dsr mode
703 * - MIPIDisplayOn - MIPIDisplayOn
704 * - wait t5 - wait t5
705 * - backlight on - MIPIBacklightOn - backlight on
707 * - backlight off - MIPIBacklightOff - backlight off
708 * - wait t6 - wait t6
709 * - MIPIDisplayOff
710 * - turn off DPI - turn off DPI - disable pipe dsr mode
711 * - MIPITearOff
712 * - MIPIDisplayOff - MIPIDisplayOff
713 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
714 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
715 * - wait t3 - wait t3
716 * - power off - MIPIPanelPowerOff - power off
717 * - wait t4 - wait t4
731 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_pre_enable()
732 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable()
733 enum pipe pipe = crtc->pipe; in intel_dsi_pre_enable()
737 drm_dbg_kms(display->drm, "\n"); in intel_dsi_pre_enable()
756 /* Add MIPI IO reset programming for modeset */ in intel_dsi_pre_enable()
773 /* Give the panel time to power-on and then deassert its reset */ in intel_dsi_pre_enable()
775 msleep(intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
786 /* Put device in ready state (LP-11) */ in intel_dsi_pre_enable()
797 * Enable port in pre-enable phase itself because as per hw team in intel_dsi_pre_enable()
801 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
808 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
838 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dsi_disable()
842 drm_dbg_kms(&i915->drm, "\n"); in intel_dsi_disable()
854 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
862 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready()
876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable()
880 drm_dbg_kms(display->drm, "\n"); in intel_dsi_post_disable()
889 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_post_disable()
906 /* Transition to LP-00 */ in intel_dsi_post_disable()
915 /* Add MIPI IO reset programming for modeset */ in intel_dsi_post_disable()
931 msleep(intel_dsi->panel_off_delay); in intel_dsi_post_disable()
934 intel_dsi->panel_power_off_time = ktime_get_boottime(); in intel_dsi_post_disable()
941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state()
947 drm_dbg_kms(display->drm, "\n"); in intel_dsi_get_hw_state()
950 encoder->power_domain); in intel_dsi_get_hw_state()
957 * machine. See BSpec North Display Engine registers/MIPI[BXT]. in intel_dsi_get_hw_state()
964 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_get_hw_state()
969 * Due to some hardware limitations on VLV/CHV, the DPI enable in intel_dsi_get_hw_state()
996 if (drm_WARN_ON(display->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1009 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1019 &pipe_config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1021 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in bxt_dsi_get_pipe_config()
1023 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config()
1032 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1035 * Atleast one port is active as encoder->get_config called only if in bxt_dsi_get_pipe_config()
1036 * encoder->get_hw_state() returns true. in bxt_dsi_get_pipe_config()
1038 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_get_pipe_config()
1047 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
1050 pipe_config->mode_flags |= in bxt_dsi_get_pipe_config()
1054 adjusted_mode->crtc_hdisplay = in bxt_dsi_get_pipe_config()
1057 adjusted_mode->crtc_vdisplay = in bxt_dsi_get_pipe_config()
1060 adjusted_mode->crtc_vtotal = in bxt_dsi_get_pipe_config()
1064 hactive = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1068 * Meaningful for video mode non-burst sync pulse mode only, in bxt_dsi_get_pipe_config()
1069 * can be zero for non-burst sync events and burst modes in bxt_dsi_get_pipe_config()
1076 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1078 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1080 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1082 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1092 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; in bxt_dsi_get_pipe_config()
1093 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1094 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1095 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1096 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in bxt_dsi_get_pipe_config()
1098 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1099 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; in bxt_dsi_get_pipe_config()
1100 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1101 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in bxt_dsi_get_pipe_config()
1115 hfp_sw = adjusted_mode_sw->crtc_hsync_start - in bxt_dsi_get_pipe_config()
1116 adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1117 hsync_sw = adjusted_mode_sw->crtc_hsync_end - in bxt_dsi_get_pipe_config()
1118 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1119 hbp_sw = adjusted_mode_sw->crtc_htotal - in bxt_dsi_get_pipe_config()
1120 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1122 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1129 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1131 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1133 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1137 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1139 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1141 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1143 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1149 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + in bxt_dsi_get_pipe_config()
1151 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1153 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1156 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) in bxt_dsi_get_pipe_config()
1157 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; in bxt_dsi_get_pipe_config()
1159 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) in bxt_dsi_get_pipe_config()
1160 adjusted_mode->crtc_hsync_start = in bxt_dsi_get_pipe_config()
1161 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1163 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) in bxt_dsi_get_pipe_config()
1164 adjusted_mode->crtc_hsync_end = in bxt_dsi_get_pipe_config()
1165 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1167 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) in bxt_dsi_get_pipe_config()
1168 adjusted_mode->crtc_hblank_start = in bxt_dsi_get_pipe_config()
1169 adjusted_mode_sw->crtc_hblank_start; in bxt_dsi_get_pipe_config()
1171 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) in bxt_dsi_get_pipe_config()
1172 adjusted_mode->crtc_hblank_end = in bxt_dsi_get_pipe_config()
1173 adjusted_mode_sw->crtc_hblank_end; in bxt_dsi_get_pipe_config()
1179 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config()
1183 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1185 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in intel_dsi_get_config()
1194 pipe_config->port_clock = pclk; in intel_dsi_get_config()
1197 pipe_config->hw.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
1198 if (intel_dsi->dual_link) in intel_dsi_get_config()
1199 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in intel_dsi_get_config()
1220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in set_dsi_timings()
1223 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in set_dsi_timings()
1224 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings()
1228 hactive = adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1229 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1230 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; in set_dsi_timings()
1231 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; in set_dsi_timings()
1233 if (intel_dsi->dual_link) { in set_dsi_timings()
1235 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in set_dsi_timings()
1236 hactive += intel_dsi->pixel_overlap; in set_dsi_timings()
1242 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; in set_dsi_timings()
1243 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; in set_dsi_timings()
1244 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; in set_dsi_timings()
1248 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1249 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1251 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1252 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1254 for_each_dsi_port(port, intel_dsi->ports) { in set_dsi_timings()
1257 * Program hdisplay and vdisplay on MIPI transcoder. in set_dsi_timings()
1263 adjusted_mode->crtc_hdisplay); in set_dsi_timings()
1265 adjusted_mode->crtc_vdisplay); in set_dsi_timings()
1267 adjusted_mode->crtc_vtotal); in set_dsi_timings()
1274 /* meaningful for video mode non-burst sync pulse mode only, in set_dsi_timings()
1275 * can be zero for non-burst sync events and burst modes */ in set_dsi_timings()
1309 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_prepare()
1310 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_prepare()
1312 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_prepare()
1314 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_prepare()
1318 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1320 mode_hdisplay = adjusted_mode->crtc_hdisplay; in intel_dsi_prepare()
1322 if (intel_dsi->dual_link) { in intel_dsi_prepare()
1324 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in intel_dsi_prepare()
1325 mode_hdisplay += intel_dsi->pixel_overlap; in intel_dsi_prepare()
1328 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1345 enum pipe pipe = crtc->pipe; in intel_dsi_prepare()
1356 intel_dsi->dphy_reg); in intel_dsi_prepare()
1359 …adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT… in intel_dsi_prepare()
1364 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
1366 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1369 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1370 val |= pixel_format_to_reg(intel_dsi->pixel_format); in intel_dsi_prepare()
1374 if (intel_dsi->eotp_pkt == 0) in intel_dsi_prepare()
1376 if (intel_dsi->clock_stop) in intel_dsi_prepare()
1385 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1392 * In burst mode, value greater than one DPI line Time in byte in intel_dsi_prepare()
1396 * In non-burst mode, Value greater than one DPI frame time in in intel_dsi_prepare()
1406 intel_dsi->video_mode == BURST_MODE) { in intel_dsi_prepare()
1408 …txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) +… in intel_dsi_prepare()
1411 …txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, i… in intel_dsi_prepare()
1414 intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
1416 intel_dsi->turn_arnd_val); in intel_dsi_prepare()
1418 intel_dsi->rst_timer_val); in intel_dsi_prepare()
1424 txclkesc(intel_dsi->escape_clk_div, 100)); in intel_dsi_prepare()
1427 !intel_dsi->dual_link) { in intel_dsi_prepare()
1436 intel_dsi->init_count); in intel_dsi_prepare()
1444 intel_dsi->init_count); in intel_dsi_prepare()
1452 intel_dsi->hs_to_lp_count); in intel_dsi_prepare()
1461 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1465 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1468 intel_dsi->dphy_reg); in intel_dsi_prepare()
1477 intel_dsi->bw_timer); in intel_dsi_prepare()
1480 …intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_… in intel_dsi_prepare()
1483 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; in intel_dsi_prepare()
1492 switch (intel_dsi->video_mode) { in intel_dsi_prepare()
1494 MISSING_CASE(intel_dsi->video_mode); in intel_dsi_prepare()
1515 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare()
1522 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_unprepare()
1545 struct drm_i915_private *i915 = to_i915(connector->dev); in vlv_dsi_mode_valid()
1581 intel_attach_scaling_mode_property(&connector->base); in vlv_dsi_add_properties()
1583 drm_connector_set_panel_orientation_with_quirk(&connector->base, in vlv_dsi_add_properties()
1585 fixed_mode->hdisplay, in vlv_dsi_add_properties()
1586 fixed_mode->vdisplay); in vlv_dsi_add_properties()
1598 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in vlv_dphy_param_init()
1599 struct intel_connector *connector = intel_dsi->attached_connector; in vlv_dphy_param_init()
1600 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in vlv_dphy_param_init()
1611 switch (intel_dsi->lane_count) { in vlv_dphy_param_init()
1629 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; in vlv_dphy_param_init()
1630 ths_prepare_hszero = mipi_config->ths_prepare_hszero; in vlv_dphy_param_init()
1636 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); in vlv_dphy_param_init()
1648 ths_prepare_ns = max(mipi_config->ths_prepare, in vlv_dphy_param_init()
1649 mipi_config->tclk_prepare); in vlv_dphy_param_init()
1655 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1662 (ths_prepare_hszero - ths_prepare_ns) * ui_den, in vlv_dphy_param_init()
1676 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1683 (tclk_prepare_clkzero - ths_prepare_ns) in vlv_dphy_param_init()
1687 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1693 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in vlv_dphy_param_init()
1697 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1703 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | in vlv_dphy_param_init()
1710 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count in vlv_dphy_param_init()
1724 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); in vlv_dphy_param_init()
1726 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); in vlv_dphy_param_init()
1727 intel_dsi->hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1730 /* LP -> HS for clock lanes in vlv_dphy_param_init()
1738 intel_dsi->clk_lp_to_hs_count = in vlv_dphy_param_init()
1744 intel_dsi->clk_lp_to_hs_count += extra_byte_count; in vlv_dphy_param_init()
1746 /* HS->LP for Clock Lanes in vlv_dphy_param_init()
1753 intel_dsi->clk_hs_to_lp_count = in vlv_dphy_param_init()
1756 intel_dsi->clk_hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1771 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1777 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); in vlv_dsi_asus_tf103c_mode_fixup()
1779 if (fixed_mode->vtotal == 820) in vlv_dsi_asus_tf103c_mode_fixup()
1780 fixed_mode->vtotal -= 4; in vlv_dsi_asus_tf103c_mode_fixup()
1785 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1786 * which under Linux become bus 0 - 6. And the MIPI sequence reference
1790 * given in the I2C MIPI sequence element. Since on other
1791 * devices the I2C bus-numbers used in the MIPI sequences do
1798 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1803 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1804 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1806 intel_dsi->i2c_bus_num = 2; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1812 if (fixed_mode->hdisplay == 1920) { in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1813 info->width_mm = 216; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1814 info->height_mm = 135; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1816 info->width_mm = 107; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1817 info->height_mm = 171; in vlv_dsi_lenovo_yoga_tab2_size_fixup()
1822 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1825 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on.
1828 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1833 /* Header Seq-id 7, length after header 11 bytes */ in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1835 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */ in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1840 struct intel_connector *connector = intel_dsi->attached_connector; in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1842 intel_dsi->i2c_bus_num = 0; in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1843 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence; in vlv_dsi_lenovo_yoga_tab3_backlight_fixup()
1863 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1870 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1873 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1882 struct intel_display *display = &dev_priv->display; in vlv_dsi_init()
1891 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1893 /* There is no detection method for MIPI so rely on VBT */ in vlv_dsi_init()
1898 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1900 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1912 encoder = &intel_dsi->base; in vlv_dsi_init()
1913 intel_dsi->attached_connector = connector; in vlv_dsi_init()
1915 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs, in vlv_dsi_init()
1918 encoder->compute_config = intel_dsi_compute_config; in vlv_dsi_init()
1919 encoder->pre_enable = intel_dsi_pre_enable; in vlv_dsi_init()
1921 encoder->enable = bxt_dsi_enable; in vlv_dsi_init()
1922 encoder->disable = intel_dsi_disable; in vlv_dsi_init()
1923 encoder->post_disable = intel_dsi_post_disable; in vlv_dsi_init()
1924 encoder->get_hw_state = intel_dsi_get_hw_state; in vlv_dsi_init()
1925 encoder->get_config = intel_dsi_get_config; in vlv_dsi_init()
1926 encoder->update_pipe = intel_backlight_update; in vlv_dsi_init()
1927 encoder->shutdown = intel_dsi_shutdown; in vlv_dsi_init()
1929 connector->get_hw_state = intel_connector_get_hw_state; in vlv_dsi_init()
1931 encoder->port = port; in vlv_dsi_init()
1932 encoder->type = INTEL_OUTPUT_DSI; in vlv_dsi_init()
1933 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in vlv_dsi_init()
1934 encoder->cloneable = 0; in vlv_dsi_init()
1937 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI in vlv_dsi_init()
1941 encoder->pipe_mask = ~0; in vlv_dsi_init()
1943 encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1945 encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
1947 intel_dsi->panel_power_off_time = ktime_get_boottime(); in vlv_dsi_init()
1949 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL); in vlv_dsi_init()
1951 if (connector->panel.vbt.dsi.config->dual_link) in vlv_dsi_init()
1952 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); in vlv_dsi_init()
1954 intel_dsi->ports = BIT(port); in vlv_dsi_init()
1956 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1957 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in vlv_dsi_init()
1959 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in vlv_dsi_init()
1960 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in vlv_dsi_init()
1963 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_init()
1971 intel_dsi->dsi_hosts[port] = host; in vlv_dsi_init()
1975 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1979 /* Use clock read-back from current hw-state for fastboot */ in vlv_dsi_init()
1982 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1983 intel_dsi->pclk, current_mode->clock); in vlv_dsi_init()
1984 if (intel_fuzzy_clock_check(intel_dsi->pclk, in vlv_dsi_init()
1985 current_mode->clock)) { in vlv_dsi_init()
1986 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1987 intel_dsi->pclk = current_mode->clock; in vlv_dsi_init()
1998 drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs, in vlv_dsi_init()
2001 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs); in vlv_dsi_init()
2003 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ in vlv_dsi_init()
2007 mutex_lock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
2009 mutex_unlock(&dev_priv->drm.mode_config.mutex); in vlv_dsi_init()
2012 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()
2019 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data; in vlv_dsi_init()
2033 drm_connector_cleanup(&connector->base); in vlv_dsi_init()
2035 drm_encoder_cleanup(&encoder->base); in vlv_dsi_init()