26 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_source_support()  local
29 	if (!HAS_DSC(display))  in intel_dsc_source_support()
32 	if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)  in intel_dsc_source_support()
43 bool intel_dsc_get_slice_config(struct intel_display *display,  in intel_dsc_get_slice_config()  argument
56 		if (!HAS_DSC_3ENGINES(display) || pipes_per_line != 4)  in intel_dsc_get_slice_config()
92 	struct intel_display *display = to_intel_display(crtc);  in is_pipe_dsc()  local
94 	if (DISPLAY_VER(display) >= 12)  in is_pipe_dsc()
103 	drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);  in is_pipe_dsc()
326 	struct intel_display *display = to_intel_display(pipe_config);  in intel_dsc_compute_params()  local
340 		drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");  in intel_dsc_compute_params()
351 	if (DISPLAY_VER(display) >= 14 &&  in intel_dsc_compute_params()
372 		drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",  in intel_dsc_compute_params()
395 	if (DISPLAY_VER(display) >= 13 && !is_dsi_dsc_1_1(pipe_config)) {  in intel_dsc_compute_params()
436 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_enabled_on_link()  local
438 	drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&  in intel_dsc_enabled_on_link()
447 	struct intel_display *display = to_intel_display(crtc);  in intel_dsc_power_domain()  local
461 	if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&  in intel_dsc_power_domain()
508 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_pps_write()  local
515 	drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);  in intel_dsc_pps_write()
520 		intel_de_write(display, dsc_reg[i], pps_val);  in intel_dsc_pps_write()
525 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_pps_configure()  local
620 	if (DISPLAY_VER(display) >= 14) {  in intel_dsc_pps_configure()
638 		intel_de_write(display, DSCA_RC_BUF_THRESH_0,  in intel_dsc_pps_configure()
640 		intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,  in intel_dsc_pps_configure()
642 		intel_de_write(display, DSCA_RC_BUF_THRESH_1,  in intel_dsc_pps_configure()
644 		intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,  in intel_dsc_pps_configure()
647 			intel_de_write(display, DSCC_RC_BUF_THRESH_0,  in intel_dsc_pps_configure()
649 			intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,  in intel_dsc_pps_configure()
651 			intel_de_write(display, DSCC_RC_BUF_THRESH_1,  in intel_dsc_pps_configure()
653 			intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,  in intel_dsc_pps_configure()
657 		intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),  in intel_dsc_pps_configure()
659 		intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),  in intel_dsc_pps_configure()
661 		intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),  in intel_dsc_pps_configure()
663 		intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),  in intel_dsc_pps_configure()
666 			intel_de_write(display,  in intel_dsc_pps_configure()
669 			intel_de_write(display,  in intel_dsc_pps_configure()
672 			intel_de_write(display,  in intel_dsc_pps_configure()
675 			intel_de_write(display,  in intel_dsc_pps_configure()
692 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,  in intel_dsc_pps_configure()
694 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,  in intel_dsc_pps_configure()
696 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,  in intel_dsc_pps_configure()
698 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,  in intel_dsc_pps_configure()
700 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,  in intel_dsc_pps_configure()
702 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,  in intel_dsc_pps_configure()
704 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,  in intel_dsc_pps_configure()
706 		intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,  in intel_dsc_pps_configure()
709 			intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,  in intel_dsc_pps_configure()
711 			intel_de_write(display,  in intel_dsc_pps_configure()
714 			intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,  in intel_dsc_pps_configure()
716 			intel_de_write(display,  in intel_dsc_pps_configure()
719 			intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,  in intel_dsc_pps_configure()
721 			intel_de_write(display,  in intel_dsc_pps_configure()
724 			intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,  in intel_dsc_pps_configure()
726 			intel_de_write(display,  in intel_dsc_pps_configure()
731 		intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),  in intel_dsc_pps_configure()
733 		intel_de_write(display,  in intel_dsc_pps_configure()
736 		intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),  in intel_dsc_pps_configure()
738 		intel_de_write(display,  in intel_dsc_pps_configure()
741 		intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),  in intel_dsc_pps_configure()
743 		intel_de_write(display,  in intel_dsc_pps_configure()
746 		intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),  in intel_dsc_pps_configure()
748 		intel_de_write(display,  in intel_dsc_pps_configure()
752 			intel_de_write(display,  in intel_dsc_pps_configure()
755 			intel_de_write(display,  in intel_dsc_pps_configure()
758 			intel_de_write(display,  in intel_dsc_pps_configure()
761 			intel_de_write(display,  in intel_dsc_pps_configure()
764 			intel_de_write(display,  in intel_dsc_pps_configure()
767 			intel_de_write(display,  in intel_dsc_pps_configure()
770 			intel_de_write(display,  in intel_dsc_pps_configure()
773 			intel_de_write(display,  in intel_dsc_pps_configure()
826 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_su_et_parameters_configure()  local
834 	drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);  in intel_dsc_su_et_parameters_configure()
835 	drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);  in intel_dsc_su_et_parameters_configure()
840 	intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);  in intel_dsc_su_et_parameters_configure()
843 		intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);  in intel_dsc_su_et_parameters_configure()
860 	struct intel_display *display = to_intel_display(crtc_state);  in intel_uncompressed_joiner_enable()  local
870 		intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),  in intel_uncompressed_joiner_enable()
877 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_enable()  local
911 	intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);  in intel_dsc_enable()
912 	intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);  in intel_dsc_enable()
917 	struct intel_display *display = to_intel_display(old_crtc_state);  in intel_dsc_disable()  local
923 		intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);  in intel_dsc_disable()
924 		intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);  in intel_dsc_disable()
931 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_pps_read()  local
939 	drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);  in intel_dsc_pps_read()
945 	val = intel_de_read(display, dsc_reg[0]);  in intel_dsc_pps_read()
948 		if (intel_de_read(display, dsc_reg[i]) != val) {  in intel_dsc_pps_read()
959 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_pps_read_and_verify()  local
964 	drm_WARN_ON(display->drm, !all_equal);  in intel_dsc_pps_read_and_verify()
971 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_get_pps_config()  local
1058 	if (DISPLAY_VER(display) >= 14) {  in intel_dsc_get_pps_config()
1074 	struct intel_display *display = to_intel_display(crtc_state);  in intel_dsc_get_config()  local
1086 	wakeref = intel_display_power_get_if_enabled(display, power_domain);  in intel_dsc_get_config()
1090 	dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));  in intel_dsc_get_config()
1091 	dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));  in intel_dsc_get_config()
1107 	intel_display_power_put(display, power_domain, wakeref);  in intel_dsc_get_config()
1130 int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,  in intel_dsc_get_pixel_rate_with_dsc_bubbles()  argument
1137 	if (drm_WARN_ON(display->drm, !htotal))  in intel_dsc_get_pixel_rate_with_dsc_bubbles()
1148 	struct intel_display *display = to_intel_display(crtc_state);  in intel_vdsc_min_cdclk()  local
1158 	pixel_rate = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,  in intel_vdsc_min_cdclk()
1187 		int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;  in intel_vdsc_min_cdclk()
1189 			intel_dsc_get_pixel_rate_with_dsc_bubbles(display, pixel_clock,  in intel_vdsc_min_cdclk()