Lines Matching defs:crtc_state
24 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
26 struct intel_display *display = to_intel_display(crtc_state);
27 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
263 static bool is_dsi_dsc_1_1(struct intel_crtc_state *crtc_state)
265 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
269 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI);
401 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
403 return crtc_state->dsc.num_streams;
406 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
408 int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
409 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
416 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
419 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
436 static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
439 struct intel_display *display = to_intel_display(crtc_state);
443 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
448 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
454 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
456 struct intel_display *display = to_intel_display(crtc_state);
457 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
458 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
465 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
466 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
488 intel_dsc_pps_write(crtc_state, 0, pps_val);
492 intel_dsc_pps_write(crtc_state, 1, pps_val);
497 intel_dsc_pps_write(crtc_state, 2, pps_val);
502 intel_dsc_pps_write(crtc_state, 3, pps_val);
507 intel_dsc_pps_write(crtc_state, 4, pps_val);
512 intel_dsc_pps_write(crtc_state, 5, pps_val);
519 intel_dsc_pps_write(crtc_state, 6, pps_val);
524 intel_dsc_pps_write(crtc_state, 7, pps_val);
529 intel_dsc_pps_write(crtc_state, 8, pps_val);
534 intel_dsc_pps_write(crtc_state, 9, pps_val);
541 intel_dsc_pps_write(crtc_state, 10, pps_val);
549 intel_dsc_pps_write(crtc_state, 16, pps_val);
554 intel_dsc_pps_write(crtc_state, 17, pps_val);
559 intel_dsc_pps_write(crtc_state, 18, pps_val);
712 const struct intel_crtc_state *crtc_state)
714 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
720 if (!crtc_state->dsc.compression_enable)
734 const struct intel_crtc_state *crtc_state)
737 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
740 if (!crtc_state->dsc.compression_enable)
749 dig_port->write_infoframe(encoder, crtc_state,
766 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
768 struct intel_display *display = to_intel_display(crtc_state);
769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
772 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
773 if (intel_crtc_is_bigjoiner_secondary(crtc_state))
778 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
783 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
785 struct intel_display *display = to_intel_display(crtc_state);
786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
789 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
791 if (!crtc_state->dsc.compression_enable)
794 intel_dsc_pps_configure(crtc_state);
807 if (crtc_state->joiner_pipes) {
808 if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
811 if (intel_crtc_is_ultrajoiner_primary(crtc_state))
816 if (intel_crtc_is_bigjoiner_primary(crtc_state))
819 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
820 intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
836 static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
839 struct intel_display *display = to_intel_display(crtc_state);
844 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
849 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
865 static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
867 struct intel_display *display = to_intel_display(crtc_state);
871 val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
877 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
879 struct intel_display *display = to_intel_display(crtc_state);
880 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
881 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
885 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
897 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
904 crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
907 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
913 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
919 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
925 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
931 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
939 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
945 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
951 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
956 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
962 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
968 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
973 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
980 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
982 struct intel_display *display = to_intel_display(crtc_state);
983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
984 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
989 if (!intel_dsc_source_support(crtc_state))
1001 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
1002 if (!crtc_state->dsc.compression_enable)
1006 crtc_state->dsc.num_streams = 3;
1008 crtc_state->dsc.num_streams = 2;
1010 crtc_state->dsc.num_streams = 1;
1012 intel_dsc_get_pps_config(crtc_state);
1018 const struct intel_crtc_state *crtc_state)
1022 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
1023 crtc_state->dsc.slice_count,
1024 crtc_state->dsc.num_streams);
1028 const struct intel_crtc_state *crtc_state)
1030 if (!crtc_state->dsc.compression_enable)
1033 intel_vdsc_dump_state(p, indent, crtc_state);
1034 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
1037 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
1039 struct intel_display *display = to_intel_display(crtc_state);
1040 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
1043 if (!crtc_state->dsc.compression_enable)
1053 min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
1055 if (crtc_state->joiner_pipes) {
1056 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
1072 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *