14 #define   DVS_PIPE_GAMMA_ENABLE		REG_BIT(30)
57 #define   DVS_WIDTH(w)			REG_FIELD_PREP(DVS_WIDTH_MASK, (w))  argument
96 #define   DVS_FILTER_MASK		REG_GENMASK(30, 29)
103 #define   DVS_SRC_WIDTH(w)		REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))  argument
120 #define   SPRITE_PIPE_GAMMA_ENABLE		REG_BIT(30)
167 #define   SPRITE_WIDTH(w)	REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))  argument
206 #define   SPRITE_FILTER_MASK			REG_GENMASK(30, 29)
213 #define   SPRITE_SRC_WIDTH(w)			REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))  argument
239 #define   SP_PIPE_GAMMA_ENABLE		REG_BIT(30)
286 #define   SP_WIDTH(w)			REG_FIELD_PREP(SP_WIDTH_MASK, (w))  argument
367 #define  SPCSC_C1_MASK		REG_GENMASK(30, 16)