Lines Matching refs:display
230 struct intel_display *display = to_intel_display(intel_dp); in psr_global_enabled() local
235 if (display->params.enable_psr == -1) in psr_global_enabled()
239 return display->params.enable_psr; in psr_global_enabled()
249 struct intel_display *display = to_intel_display(intel_dp); in psr2_global_enabled() local
256 if (display->params.enable_psr == 1) in psr2_global_enabled()
264 struct intel_display *display = to_intel_display(intel_dp); in psr2_su_region_et_global_enabled() local
266 if (display->params.enable_psr != -1) in psr2_su_region_et_global_enabled()
274 struct intel_display *display = to_intel_display(intel_dp); in panel_replay_global_enabled() local
276 if ((display->params.enable_psr != -1) || in panel_replay_global_enabled()
284 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_psr_error_bit_get() local
286 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : in psr_irq_psr_error_bit_get()
292 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_post_exit_bit_get() local
294 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : in psr_irq_post_exit_bit_get()
300 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_pre_entry_bit_get() local
302 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : in psr_irq_pre_entry_bit_get()
308 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_mask_get() local
310 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : in psr_irq_mask_get()
314 static i915_reg_t psr_ctl_reg(struct intel_display *display, in psr_ctl_reg() argument
317 if (DISPLAY_VER(display) >= 8) in psr_ctl_reg()
318 return EDP_PSR_CTL(display, cpu_transcoder); in psr_ctl_reg()
323 static i915_reg_t psr_debug_reg(struct intel_display *display, in psr_debug_reg() argument
326 if (DISPLAY_VER(display) >= 8) in psr_debug_reg()
327 return EDP_PSR_DEBUG(display, cpu_transcoder); in psr_debug_reg()
332 static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, in psr_perf_cnt_reg() argument
335 if (DISPLAY_VER(display) >= 8) in psr_perf_cnt_reg()
336 return EDP_PSR_PERF_CNT(display, cpu_transcoder); in psr_perf_cnt_reg()
341 static i915_reg_t psr_status_reg(struct intel_display *display, in psr_status_reg() argument
344 if (DISPLAY_VER(display) >= 8) in psr_status_reg()
345 return EDP_PSR_STATUS(display, cpu_transcoder); in psr_status_reg()
350 static i915_reg_t psr_imr_reg(struct intel_display *display, in psr_imr_reg() argument
353 if (DISPLAY_VER(display) >= 12) in psr_imr_reg()
354 return TRANS_PSR_IMR(display, cpu_transcoder); in psr_imr_reg()
359 static i915_reg_t psr_iir_reg(struct intel_display *display, in psr_iir_reg() argument
362 if (DISPLAY_VER(display) >= 12) in psr_iir_reg()
363 return TRANS_PSR_IIR(display, cpu_transcoder); in psr_iir_reg()
368 static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, in psr_aux_ctl_reg() argument
371 if (DISPLAY_VER(display) >= 8) in psr_aux_ctl_reg()
372 return EDP_PSR_AUX_CTL(display, cpu_transcoder); in psr_aux_ctl_reg()
377 static i915_reg_t psr_aux_data_reg(struct intel_display *display, in psr_aux_data_reg() argument
380 if (DISPLAY_VER(display) >= 8) in psr_aux_data_reg()
381 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); in psr_aux_data_reg()
388 struct intel_display *display = to_intel_display(intel_dp); in psr_irq_control() local
400 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), in psr_irq_control()
404 static void psr_event_print(struct intel_display *display, in psr_event_print() argument
407 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); in psr_event_print()
409 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); in psr_event_print()
411 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); in psr_event_print()
413 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); in psr_event_print()
415 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); in psr_event_print()
417 drm_dbg_kms(display->drm, "\tGraphics reset\n"); in psr_event_print()
419 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); in psr_event_print()
421 drm_dbg_kms(display->drm, "\tMemory up\n"); in psr_event_print()
423 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); in psr_event_print()
425 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); in psr_event_print()
427 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); in psr_event_print()
429 drm_dbg_kms(display->drm, "\tRegister updated\n"); in psr_event_print()
431 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); in psr_event_print()
433 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); in psr_event_print()
435 drm_dbg_kms(display->drm, "\tVBI enabled\n"); in psr_event_print()
437 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); in psr_event_print()
439 drm_dbg_kms(display->drm, "\tPSR disabled\n"); in psr_event_print()
444 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_irq_handler() local
445 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_irq_handler()
451 drm_dbg_kms(display->drm, in intel_psr_irq_handler()
458 drm_dbg_kms(display->drm, in intel_psr_irq_handler()
462 if (DISPLAY_VER(display) >= 9) { in intel_psr_irq_handler()
469 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); in intel_psr_irq_handler()
474 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", in intel_psr_irq_handler()
487 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), in intel_psr_irq_handler()
496 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_get_sink_sync_latency() local
503 drm_dbg_kms(display->drm, in intel_dp_get_sink_sync_latency()
544 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_get_su_granularity() local
570 drm_dbg_kms(display->drm, in intel_dp_get_su_granularity()
583 drm_dbg_kms(display->drm, in intel_dp_get_su_granularity()
597 struct intel_display *display = to_intel_display(intel_dp); in _panel_replay_init_dpcd() local
601 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
607 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
618 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
626 struct intel_display *display = to_intel_display(intel_dp); in _psr_init_dpcd() local
628 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", in _psr_init_dpcd()
632 drm_dbg_kms(display->drm, in _psr_init_dpcd()
638 drm_dbg_kms(display->drm, in _psr_init_dpcd()
647 if (DISPLAY_VER(display) >= 9 && in _psr_init_dpcd()
665 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", in _psr_init_dpcd()
690 struct intel_display *display = to_intel_display(intel_dp); in hsw_psr_setup_aux() local
691 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_psr_setup_aux()
707 psr_aux_data_reg(display, cpu_transcoder, i >> 2), in hsw_psr_setup_aux()
722 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), in hsw_psr_setup_aux()
728 struct intel_display *display = to_intel_display(intel_dp); in psr2_su_region_et_valid() local
730 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || in psr2_su_region_et_valid()
769 struct intel_display *display = to_intel_display(intel_dp); in _psr_enable_sink() local
778 if (DISPLAY_VER(display) >= 8) in _psr_enable_sink()
832 struct intel_display *display = to_intel_display(intel_dp); in intel_psr1_get_tp_time() local
834 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr1_get_tp_time()
837 if (DISPLAY_VER(display) >= 11) in intel_psr1_get_tp_time()
840 if (display->params.psr_safest_params) { in intel_psr1_get_tp_time()
885 struct intel_display *display = to_intel_display(intel_dp); in psr_compute_idle_frames() local
895 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) in psr_compute_idle_frames()
903 struct intel_display *display = to_intel_display(intel_dp); in hsw_activate_psr1() local
904 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_activate_psr1()
911 if (DISPLAY_VER(display) < 20) in hsw_activate_psr1()
922 if (DISPLAY_VER(display) >= 8) in hsw_activate_psr1()
925 if (DISPLAY_VER(display) >= 20) in hsw_activate_psr1()
928 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), in hsw_activate_psr1()
934 struct intel_display *display = to_intel_display(intel_dp); in intel_psr2_get_tp_time() local
938 if (display->params.psr_safest_params) in intel_psr2_get_tp_time()
982 struct intel_display *display = to_intel_display(intel_dp); in dg2_activate_panel_replay() local
993 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), in dg2_activate_panel_replay()
997 intel_de_rmw(display, in dg2_activate_panel_replay()
998 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), in dg2_activate_panel_replay()
1001 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, in dg2_activate_panel_replay()
1007 struct intel_display *display = to_intel_display(intel_dp); in hsw_activate_psr2() local
1008 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_activate_psr2()
1015 if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv)) in hsw_activate_psr2()
1018 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) in hsw_activate_psr2()
1025 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { in hsw_activate_psr2()
1033 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) { in hsw_activate_psr2()
1056 } else if (DISPLAY_VER(display) >= 20) { in hsw_activate_psr2()
1058 } else if (DISPLAY_VER(display) >= 12) { in hsw_activate_psr2()
1061 } else if (DISPLAY_VER(display) >= 9) { in hsw_activate_psr2()
1069 if (DISPLAY_VER(display) >= 20) in hsw_activate_psr2()
1075 tmp = intel_de_read(display, in hsw_activate_psr2()
1076 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); in hsw_activate_psr2()
1077 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); in hsw_activate_psr2()
1078 } else if (HAS_PSR2_SEL_FETCH(display)) { in hsw_activate_psr2()
1079 intel_de_write(display, in hsw_activate_psr2()
1080 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); in hsw_activate_psr2()
1090 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); in hsw_activate_psr2()
1092 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); in hsw_activate_psr2()
1096 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) in transcoder_has_psr2() argument
1098 struct drm_i915_private *dev_priv = to_i915(display->drm); in transcoder_has_psr2()
1100 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) in transcoder_has_psr2()
1102 else if (DISPLAY_VER(display) >= 12) in transcoder_has_psr2()
1104 else if (DISPLAY_VER(display) >= 9) in transcoder_has_psr2()
1122 struct intel_display *display = to_intel_display(intel_dp); in psr2_program_idle_frames() local
1125 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), in psr2_program_idle_frames()
1132 struct intel_display *display = to_intel_display(intel_dp); in tgl_psr2_enable_dc3co() local
1133 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_psr2_enable_dc3co()
1141 struct intel_display *display = to_intel_display(intel_dp); in tgl_psr2_disable_dc3co() local
1142 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_psr2_disable_dc3co()
1177 struct intel_display *display = to_intel_display(intel_dp); in dc3co_is_pipe_port_compatible() local
1180 struct drm_i915_private *dev_priv = to_i915(display->drm); in dc3co_is_pipe_port_compatible()
1183 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) in dc3co_is_pipe_port_compatible()
1193 struct intel_display *display = to_intel_display(intel_dp); in tgl_dc3co_exitline_compute_config() local
1194 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_dc3co_exitline_compute_config()
1196 struct i915_power_domains *power_domains = &display->power.domains; in tgl_dc3co_exitline_compute_config()
1220 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) in tgl_dc3co_exitline_compute_config()
1230 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) in tgl_dc3co_exitline_compute_config()
1239 struct intel_display *display = to_intel_display(intel_dp); in intel_psr2_sel_fetch_config_valid() local
1241 if (!display->params.enable_psr2_sel_fetch && in intel_psr2_sel_fetch_config_valid()
1243 drm_dbg_kms(display->drm, in intel_psr2_sel_fetch_config_valid()
1249 drm_dbg_kms(display->drm, in intel_psr2_sel_fetch_config_valid()
1260 struct intel_display *display = to_intel_display(intel_dp); in psr2_granularity_check() local
1261 struct drm_i915_private *dev_priv = to_i915(display->drm); in psr2_granularity_check()
1283 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) in psr2_granularity_check()
1304 struct intel_display *display = to_intel_display(intel_dp); in _compute_psr2_sdp_prior_scanline_indication() local
1318 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) in _compute_psr2_sdp_prior_scanline_indication()
1328 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_entry_setup_frames() local
1333 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1341 if (DISPLAY_VER(display) >= 20) { in intel_psr_entry_setup_frames()
1344 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1348 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1362 struct intel_display *display = to_intel_display(intel_dp); in wake_lines_fit_into_vblank() local
1370 wake_lines = DISPLAY_VER(display) < 20 ? in wake_lines_fit_into_vblank()
1388 struct intel_display *display = to_intel_display(intel_dp); in alpm_config_valid() local
1391 drm_dbg_kms(display->drm, in alpm_config_valid()
1397 drm_dbg_kms(display->drm, in alpm_config_valid()
1408 struct intel_display *display = to_intel_display(intel_dp); in intel_psr2_config_valid() local
1409 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr2_config_valid()
1419 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); in intel_psr2_config_valid()
1426 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1431 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { in intel_psr2_config_valid()
1432 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1437 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
1438 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1450 (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))) { in intel_psr2_config_valid()
1451 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1456 if (DISPLAY_VER(display) >= 20) { in intel_psr2_config_valid()
1460 } else if (IS_DISPLAY_VER(display, 12, 14)) { in intel_psr2_config_valid()
1464 } else if (IS_DISPLAY_VER(display, 10, 11)) { in intel_psr2_config_valid()
1468 } else if (DISPLAY_VER(display) == 9) { in intel_psr2_config_valid()
1475 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1483 IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { in intel_psr2_config_valid()
1484 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1494 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1509 struct intel_display *display = to_intel_display(intel_dp); in intel_sel_update_config_valid() local
1511 if (HAS_PSR2_SEL_FETCH(display) && in intel_sel_update_config_valid()
1513 !HAS_PSR_HW_TRACKING(display)) { in intel_sel_update_config_valid()
1514 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1520 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1529 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1534 if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 || in intel_sel_update_config_valid()
1539 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1545 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1563 struct intel_display *display = to_intel_display(intel_dp); in _psr_compute_config() local
1582 drm_dbg_kms(display->drm, in _psr_compute_config()
1595 struct intel_display *display = to_intel_display(intel_dp); in _panel_replay_compute_config() local
1604 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); in _panel_replay_compute_config()
1619 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1630 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1639 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1651 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_compute_config() local
1655 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); in intel_psr_compute_config()
1660 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1666 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1677 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1698 struct intel_display *display = to_intel_display(encoder); in intel_psr_get_config() local
1731 if (HAS_PSR2_SEL_FETCH(display)) { in intel_psr_get_config()
1732 val = intel_de_read(display, in intel_psr_get_config()
1733 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); in intel_psr_get_config()
1740 if (DISPLAY_VER(display) >= 12) { in intel_psr_get_config()
1741 val = intel_de_read(display, in intel_psr_get_config()
1742 TRANS_EXITLINE(display, cpu_transcoder)); in intel_psr_get_config()
1751 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_activate() local
1754 drm_WARN_ON(display->drm, in intel_psr_activate()
1755 transcoder_has_psr2(display, cpu_transcoder) && in intel_psr_activate()
1756 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); in intel_psr_activate()
1758 drm_WARN_ON(display->drm, in intel_psr_activate()
1759 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); in intel_psr_activate()
1761 drm_WARN_ON(display->drm, intel_dp->psr.active); in intel_psr_activate()
1800 struct intel_display *display = to_intel_display(intel_dp); in wm_optimization_wa() local
1804 if (IS_DISPLAY_VER(display, 11, 14)) in wm_optimization_wa()
1808 if (DISPLAY_VER(display) == 12) in wm_optimization_wa()
1813 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1816 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1823 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_enable_source() local
1824 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_enable_source()
1832 if (DISPLAY_VER(display) < 9) in intel_psr_enable_source()
1849 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) in intel_psr_enable_source()
1863 if (DISPLAY_VER(display) >= 8 || IS_HASWELL_ULT(dev_priv)) in intel_psr_enable_source()
1866 if (DISPLAY_VER(display) < 20) in intel_psr_enable_source()
1873 if (IS_DISPLAY_VER(display, 9, 10)) in intel_psr_enable_source()
1881 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); in intel_psr_enable_source()
1890 intel_de_rmw(display, in intel_psr_enable_source()
1891 TRANS_EXITLINE(display, cpu_transcoder), in intel_psr_enable_source()
1895 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) in intel_psr_enable_source()
1896 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, in intel_psr_enable_source()
1910 if (DISPLAY_VER(display) == 9) in intel_psr_enable_source()
1911 intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder), 0, in intel_psr_enable_source()
1921 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || in intel_psr_enable_source()
1923 intel_de_rmw(display, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), in intel_psr_enable_source()
1928 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) in intel_psr_enable_source()
1929 intel_de_rmw(display, in intel_psr_enable_source()
1930 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), in intel_psr_enable_source()
1934 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, in intel_psr_enable_source()
1941 struct intel_display *display = to_intel_display(intel_dp); in psr_interrupt_error_check() local
1956 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); in psr_interrupt_error_check()
1960 drm_dbg_kms(display->drm, in psr_interrupt_error_check()
1972 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_enable_locked() local
1976 drm_WARN_ON(display->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1997 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); in intel_psr_enable_locked()
1999 drm_dbg_kms(display->drm, "Enabling PSR%s\n", in intel_psr_enable_locked()
2030 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_exit() local
2035 if (transcoder_has_psr2(display, cpu_transcoder)) { in intel_psr_exit()
2036 val = intel_de_read(display, in intel_psr_exit()
2037 EDP_PSR2_CTL(display, cpu_transcoder)); in intel_psr_exit()
2038 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); in intel_psr_exit()
2041 val = intel_de_read(display, in intel_psr_exit()
2042 psr_ctl_reg(display, cpu_transcoder)); in intel_psr_exit()
2043 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); in intel_psr_exit()
2049 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), in intel_psr_exit()
2054 val = intel_de_rmw(display, in intel_psr_exit()
2055 EDP_PSR2_CTL(display, cpu_transcoder), in intel_psr_exit()
2058 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); in intel_psr_exit()
2060 val = intel_de_rmw(display, in intel_psr_exit()
2061 psr_ctl_reg(display, cpu_transcoder), in intel_psr_exit()
2064 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); in intel_psr_exit()
2071 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_wait_exit_locked() local
2078 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); in intel_psr_wait_exit_locked()
2081 psr_status = psr_status_reg(display, cpu_transcoder); in intel_psr_wait_exit_locked()
2086 if (intel_de_wait_for_clear(display, psr_status, in intel_psr_wait_exit_locked()
2088 drm_err(display->drm, "Timed out waiting PSR idle state\n"); in intel_psr_wait_exit_locked()
2093 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_disable_locked() local
2094 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_disable_locked()
2103 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); in intel_psr_disable_locked()
2105 drm_dbg_kms(display->drm, "Disabling PSR%s\n", in intel_psr_disable_locked()
2115 if (DISPLAY_VER(display) >= 11) in intel_psr_disable_locked()
2116 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in intel_psr_disable_locked()
2122 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) in intel_psr_disable_locked()
2123 intel_de_rmw(display, in intel_psr_disable_locked()
2124 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), in intel_psr_disable_locked()
2127 intel_de_rmw(display, CLKGATE_DIS_MISC, in intel_psr_disable_locked()
2136 intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), in intel_psr_disable_locked()
2140 intel_de_rmw(display, in intel_psr_disable_locked()
2172 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_disable() local
2177 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp))) in intel_psr_disable()
2199 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_pause() local
2213 drm_WARN_ON(display->drm, psr->paused); in intel_psr_pause()
2280 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) in man_trk_ctl_enable_bit_get() argument
2282 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_enable_bit_get()
2284 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? 0 : in man_trk_ctl_enable_bit_get()
2288 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) in man_trk_ctl_single_full_frame_bit_get() argument
2290 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_single_full_frame_bit_get()
2292 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? in man_trk_ctl_single_full_frame_bit_get()
2297 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) in man_trk_ctl_partial_frame_bit_get() argument
2299 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_partial_frame_bit_get()
2301 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? in man_trk_ctl_partial_frame_bit_get()
2306 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) in man_trk_ctl_continuos_full_frame() argument
2308 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_continuos_full_frame()
2310 return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? in man_trk_ctl_continuos_full_frame()
2317 struct intel_display *display = to_intel_display(intel_dp); in psr_force_hw_tracking_exit() local
2321 intel_de_write(display, in psr_force_hw_tracking_exit()
2322 PSR2_MAN_TRK_CTL(display, cpu_transcoder), in psr_force_hw_tracking_exit()
2323 man_trk_ctl_enable_bit_get(display) | in psr_force_hw_tracking_exit()
2324 man_trk_ctl_partial_frame_bit_get(display) | in psr_force_hw_tracking_exit()
2325 man_trk_ctl_single_full_frame_bit_get(display) | in psr_force_hw_tracking_exit()
2326 man_trk_ctl_continuos_full_frame(display)); in psr_force_hw_tracking_exit()
2341 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); in psr_force_hw_tracking_exit()
2346 struct intel_display *display = to_intel_display(crtc_state); in intel_psr2_program_trans_man_trk_ctl() local
2354 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr2_program_trans_man_trk_ctl()
2364 intel_de_write(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), in intel_psr2_program_trans_man_trk_ctl()
2370 intel_de_write(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), in intel_psr2_program_trans_man_trk_ctl()
2377 struct intel_display *display = to_intel_display(crtc_state); in psr2_man_trk_ctl_calc() local
2380 u32 val = man_trk_ctl_enable_bit_get(display); in psr2_man_trk_ctl_calc()
2383 val |= man_trk_ctl_partial_frame_bit_get(display); in psr2_man_trk_ctl_calc()
2386 val |= man_trk_ctl_single_full_frame_bit_get(display); in psr2_man_trk_ctl_calc()
2387 val |= man_trk_ctl_continuos_full_frame(display); in psr2_man_trk_ctl_calc()
2394 if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) { in psr2_man_trk_ctl_calc()
2447 struct intel_display *display = to_intel_display(crtc_state); in intel_psr2_sel_fetch_pipe_alignment() local
2454 (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)) in intel_psr2_sel_fetch_pipe_alignment()
2542 struct intel_display *display = to_intel_display(crtc_state); in intel_psr_apply_pr_link_on_su_wa() local
2558 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_apply_pr_link_on_su_wa()
2574 struct intel_display *display = to_intel_display(crtc_state); in intel_psr_apply_su_area_workarounds() local
2579 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || in intel_psr_apply_su_area_workarounds()
2585 if (DISPLAY_VER(display) == 30) in intel_psr_apply_su_area_workarounds()
2592 struct intel_display *display = to_intel_display(state); in intel_psr2_sel_fetch_update() local
2688 drm_info_once(display->drm, in intel_psr2_sel_fetch_update()
2780 struct intel_display *display = to_intel_display(state); in intel_psr_pre_plane_update() local
2788 if (!HAS_PSR(display)) in intel_psr_pre_plane_update()
2829 struct intel_display *display = to_intel_display(state); in intel_psr_post_plane_update() local
2845 drm_WARN_ON(display->drm, in intel_psr_post_plane_update()
2852 keep_disabled |= DISPLAY_VER(display) < 11 && in intel_psr_post_plane_update()
2877 struct intel_display *display = to_intel_display(intel_dp); in _psr2_ready_for_pipe_update_locked() local
2885 return intel_de_wait_for_clear(display, in _psr2_ready_for_pipe_update_locked()
2886 EDP_PSR2_STATUS(display, cpu_transcoder), in _psr2_ready_for_pipe_update_locked()
2892 struct intel_display *display = to_intel_display(intel_dp); in _psr1_ready_for_pipe_update_locked() local
2901 return intel_de_wait_for_clear(display, in _psr1_ready_for_pipe_update_locked()
2902 psr_status_reg(display, cpu_transcoder), in _psr1_ready_for_pipe_update_locked()
2915 struct intel_display *display = to_intel_display(new_crtc_state); in intel_psr_wait_for_idle_locked() local
2921 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_wait_for_idle_locked()
2937 drm_err(display->drm, in intel_psr_wait_for_idle_locked()
2944 struct intel_display *display = to_intel_display(intel_dp); in __psr_wait_for_idle_locked() local
2955 reg = EDP_PSR2_STATUS(display, cpu_transcoder); in __psr_wait_for_idle_locked()
2958 reg = psr_status_reg(display, cpu_transcoder); in __psr_wait_for_idle_locked()
2964 err = intel_de_wait_for_clear(display, reg, mask, 50); in __psr_wait_for_idle_locked()
2966 drm_err(display->drm, in __psr_wait_for_idle_locked()
2974 static int intel_psr_fastset_force(struct intel_display *display) in intel_psr_fastset_force() argument
2982 state = drm_atomic_state_alloc(display->drm); in intel_psr_fastset_force()
2992 drm_connector_list_iter_begin(display->drm, &conn_iter); in intel_psr_fastset_force()
3039 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_debug_set() local
3050 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); in intel_psr_debug_set()
3075 ret = intel_psr_fastset_force(display); in intel_psr_debug_set()
3127 struct intel_display *display = to_intel_display(intel_dp); in _psr_invalidate_handle() local
3135 intel_de_write(display, in _psr_invalidate_handle()
3136 CURSURFLIVE(display, intel_dp->psr.pipe), in _psr_invalidate_handle()
3141 val = man_trk_ctl_enable_bit_get(display) | in _psr_invalidate_handle()
3142 man_trk_ctl_partial_frame_bit_get(display) | in _psr_invalidate_handle()
3143 man_trk_ctl_continuos_full_frame(display); in _psr_invalidate_handle()
3144 intel_de_write(display, in _psr_invalidate_handle()
3145 PSR2_MAN_TRK_CTL(display, cpu_transcoder), in _psr_invalidate_handle()
3147 intel_de_write(display, in _psr_invalidate_handle()
3148 CURSURFLIVE(display, intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
3168 void intel_psr_invalidate(struct intel_display *display, in intel_psr_invalidate() argument
3176 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_psr_invalidate()
3206 struct intel_display *display = to_intel_display(intel_dp); in tgl_dc3co_flush_locked() local
3207 struct drm_i915_private *i915 = to_i915(display->drm); in tgl_dc3co_flush_locked()
3228 struct intel_display *display = to_intel_display(intel_dp); in _psr_flush_handle() local
3229 struct drm_i915_private *dev_priv = to_i915(display->drm); in _psr_flush_handle()
3236 u32 val = man_trk_ctl_enable_bit_get(display) | in _psr_flush_handle()
3237 man_trk_ctl_partial_frame_bit_get(display) | in _psr_flush_handle()
3238 man_trk_ctl_single_full_frame_bit_get(display) | in _psr_flush_handle()
3239 man_trk_ctl_continuos_full_frame(display); in _psr_flush_handle()
3247 intel_de_write(display, in _psr_flush_handle()
3248 PSR2_MAN_TRK_CTL(display, cpu_transcoder), in _psr_flush_handle()
3250 intel_de_write(display, in _psr_flush_handle()
3251 CURSURFLIVE(display, intel_dp->psr.pipe), in _psr_flush_handle()
3283 void intel_psr_flush(struct intel_display *display, in intel_psr_flush() argument
3288 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_psr_flush()
3337 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_init() local
3338 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_init()
3342 if (!(HAS_PSR(display) || HAS_DP20(dev_priv))) in intel_psr_init()
3354 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { in intel_psr_init()
3355 drm_dbg_kms(display->drm, in intel_psr_init()
3361 DISPLAY_VER(display) >= 20) in intel_psr_init()
3364 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) in intel_psr_init()
3368 if (DISPLAY_VER(display) < 12) in intel_psr_init()
3405 struct intel_display *display = to_intel_display(intel_dp); in psr_alpm_check() local
3416 drm_err(display->drm, "Error reading ALPM status\n"); in psr_alpm_check()
3423 drm_dbg_kms(display->drm, in psr_alpm_check()
3433 struct intel_display *display = to_intel_display(intel_dp); in psr_capability_changed_check() local
3440 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); in psr_capability_changed_check()
3447 drm_dbg_kms(display->drm, in psr_capability_changed_check()
3464 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_short_pulse() local
3482 drm_err(display->drm, in intel_psr_short_pulse()
3495 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3498 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3501 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3504 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3508 drm_err(display->drm, in intel_psr_short_pulse()
3574 struct intel_display *display = to_intel_display(crtc_state); in intel_psr_lock() local
3580 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_lock()
3597 struct intel_display *display = to_intel_display(crtc_state); in intel_psr_unlock() local
3603 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_unlock()
3615 struct intel_display *display = to_intel_display(intel_dp); in psr_source_status() local
3635 val = intel_de_read(display, in psr_source_status()
3636 EDP_PSR2_STATUS(display, cpu_transcoder)); in psr_source_status()
3651 val = intel_de_read(display, in psr_source_status()
3652 psr_status_reg(display, cpu_transcoder)); in psr_source_status()
3713 struct intel_display *display = to_intel_display(intel_dp); in intel_psr_status() local
3714 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_status()
3739 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); in intel_psr_status()
3742 psr2_ctl = intel_de_read(display, in intel_psr_status()
3743 EDP_PSR2_CTL(display, in intel_psr_status()
3748 val = intel_de_read(display, in intel_psr_status()
3749 EDP_PSR2_CTL(display, cpu_transcoder)); in intel_psr_status()
3752 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); in intel_psr_status()
3767 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); in intel_psr_status()
3786 val = intel_de_read(display, in intel_psr_status()
3787 PSR2_SU_STATUS(display, cpu_transcoder, frame)); in intel_psr_status()
3815 struct intel_display *display = m->private; in i915_edp_psr_status_show() local
3819 if (!HAS_PSR(display)) in i915_edp_psr_status_show()
3823 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_status_show()
3838 struct intel_display *display = data; in i915_edp_psr_debug_set() local
3839 struct drm_i915_private *dev_priv = to_i915(display->drm); in i915_edp_psr_debug_set()
3844 if (!HAS_PSR(display)) in i915_edp_psr_debug_set()
3847 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_debug_set()
3850 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); in i915_edp_psr_debug_set()
3866 struct intel_display *display = data; in i915_edp_psr_debug_get() local
3869 if (!HAS_PSR(display)) in i915_edp_psr_debug_get()
3872 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_debug_get()
3887 void intel_psr_debugfs_register(struct intel_display *display) in intel_psr_debugfs_register() argument
3889 struct drm_minor *minor = display->drm->primary; in intel_psr_debugfs_register()
3892 display, &i915_edp_psr_debug_fops); in intel_psr_debugfs_register()
3895 display, &i915_edp_psr_status_fops); in intel_psr_debugfs_register()
3976 struct intel_display *display = to_intel_display(connector); in intel_psr_connector_debugfs_add() local
3987 if (HAS_PSR(display) || HAS_DP20(i915)) in intel_psr_connector_debugfs_add()