Lines Matching defs:psr
198 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
199 (intel_dp)->psr.source_support)
234 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
238 connector->panel.vbt.psr.enable :
252 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
278 (intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE))
288 EDP_PSR_ERROR(intel_dp->psr.transcoder);
296 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
304 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
312 EDP_PSR_MASK(intel_dp->psr.transcoder);
390 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
393 if (intel_dp->psr.panel_replay_enabled)
397 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
447 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
451 intel_dp->psr.last_entry_attempt = time_ns;
458 intel_dp->psr.last_exit = time_ns;
470 psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
478 intel_dp->psr.irq_aux_error = true;
491 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
513 if (intel_dp->psr.sink_panel_replay_su_support)
526 return intel_dp->psr.sink_panel_replay_su_support ?
534 return intel_dp->psr.sink_panel_replay_su_support ?
540 * Note: Bits related to granularity are same in panel replay and psr
592 intel_dp->psr.su_w_granularity = w;
593 intel_dp->psr.su_y_granularity = y;
614 intel_dp->psr.sink_panel_replay_support = true;
617 intel_dp->psr.sink_panel_replay_su_support = true;
621 intel_dp->psr.sink_panel_replay_su_support ?
644 intel_dp->psr.sink_support = true;
645 intel_dp->psr.sink_sync_latency =
664 intel_dp->psr.sink_psr2_support = y_req &&
667 intel_dp->psr.sink_psr2_support ? "" : "not ");
684 if (intel_dp->psr.sink_psr2_support ||
685 intel_dp->psr.sink_panel_replay_su_support)
693 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
732 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
776 if (intel_dp->psr.link_standby)
789 if (intel_dp->psr.entry_setup_frames > 0)
854 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
856 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
858 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
863 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
865 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
867 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
877 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
878 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
900 idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
901 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
913 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
925 if (intel_dp->psr.link_standby)
934 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
949 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
950 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
952 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
954 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
978 intel_dp->psr.sink_sync_latency + 1,
982 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
983 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
991 struct intel_psr *psr = &intel_dp->psr;
992 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
994 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
995 u32 val = psr->su_region_et_enabled ?
998 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
1006 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
1009 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
1017 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1074 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
1078 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
1080 if (intel_dp->psr.psr2_sel_fetch_enabled) {
1091 if (intel_dp->psr.su_region_et_enabled)
1131 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1157 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
1159 mutex_lock(&intel_dp->psr.lock);
1161 if (delayed_work_pending(&intel_dp->psr.dc3co_work))
1166 mutex_unlock(&intel_dp->psr.lock);
1171 if (!intel_dp->psr.dc3co_exitline)
1174 cancel_delayed_work(&intel_dp->psr.dc3co_work);
1248 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
1274 if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
1277 if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
1282 return intel_dp->psr.su_y_granularity == 4;
1290 y_granularity = intel_dp->psr.su_y_granularity;
1291 else if (intel_dp->psr.su_y_granularity <= 2)
1293 else if ((intel_dp->psr.su_y_granularity % 4) == 0)
1294 y_granularity = intel_dp->psr.su_y_granularity;
1420 if (!intel_dp->psr.sink_psr2_support)
1541 !intel_dp->psr.sink_panel_replay_su_support))
1579 intel_dp->psr.entry_setup_frames = entry_setup_frames;
1651 return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 &&
1667 if (intel_dp->psr.sink_not_reliable) {
1732 mutex_lock(&intel_dp->psr.lock);
1733 if (!intel_dp->psr.enabled)
1736 if (intel_dp->psr.panel_replay_enabled) {
1746 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
1749 if (!intel_dp->psr.sel_update_enabled)
1759 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;
1767 mutex_unlock(&intel_dp->psr.lock);
1773 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1782 drm_WARN_ON(display->drm, intel_dp->psr.active);
1784 lockdep_assert_held(&intel_dp->psr.lock);
1787 if (intel_dp->psr.panel_replay_enabled)
1789 else if (intel_dp->psr.sel_update_enabled)
1794 intel_dp->psr.active = true;
1805 enum pipe pipe = intel_dp->psr.pipe;
1831 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1895 if (intel_dp->psr.dc3co_exitline)
1899 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
1903 intel_dp->psr.psr2_sel_fetch_enabled ?
1915 if (intel_dp->psr.sel_update_enabled) {
1926 if (!intel_dp->psr.panel_replay_enabled &&
1933 if (!intel_dp->psr.panel_replay_enabled &&
1948 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1951 if (intel_dp->psr.panel_replay_enabled)
1965 intel_dp->psr.sink_not_reliable = true;
1982 drm_WARN_ON(display->drm, intel_dp->psr.enabled);
1984 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
1985 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
1986 intel_dp->psr.busy_frontbuffer_bits = 0;
1987 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1988 intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1991 intel_dp->psr.dc3co_exit_delay = val;
1992 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1993 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1994 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
1995 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1996 intel_dp->psr.req_psr2_sdp_prior_scanline =
2002 if (intel_dp->psr.panel_replay_enabled)
2006 intel_dp->psr.sel_update_enabled ? "2" : "1");
2026 intel_dp->psr.enabled = true;
2027 intel_dp->psr.paused = false;
2036 intel_dp->psr.link_ok = true;
2044 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2047 if (!intel_dp->psr.active) {
2061 if (intel_dp->psr.panel_replay_enabled) {
2062 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
2064 } else if (intel_dp->psr.sel_update_enabled) {
2079 intel_dp->psr.active = false;
2085 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2089 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
2090 intel_dp->psr.panel_replay_enabled)) {
2108 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2110 lockdep_assert_held(&intel_dp->psr.lock);
2112 if (!intel_dp->psr.enabled)
2115 if (intel_dp->psr.panel_replay_enabled)
2119 intel_dp->psr.sel_update_enabled ? "2" : "1");
2130 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);
2132 if (intel_dp->psr.sel_update_enabled) {
2134 if (!intel_dp->psr.panel_replay_enabled &&
2148 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
2159 if (!intel_dp->psr.panel_replay_enabled) {
2162 if (intel_dp->psr.sel_update_enabled)
2167 intel_dp->psr.enabled = false;
2168 intel_dp->psr.panel_replay_enabled = false;
2169 intel_dp->psr.sel_update_enabled = false;
2170 intel_dp->psr.psr2_sel_fetch_enabled = false;
2171 intel_dp->psr.su_region_et_enabled = false;
2172 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2194 mutex_lock(&intel_dp->psr.lock);
2198 intel_dp->psr.link_ok = false;
2200 mutex_unlock(&intel_dp->psr.lock);
2201 cancel_work_sync(&intel_dp->psr.work);
2202 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
2209 * This function need to be called after enabling psr.
2214 struct intel_psr *psr = &intel_dp->psr;
2219 mutex_lock(&psr->lock);
2221 if (!psr->enabled) {
2222 mutex_unlock(&psr->lock);
2227 drm_WARN_ON(display->drm, psr->paused);
2231 psr->paused = true;
2233 mutex_unlock(&psr->lock);
2235 cancel_work_sync(&psr->work);
2236 cancel_delayed_work_sync(&psr->dc3co_work);
2243 * This function need to be called after pausing psr.
2247 struct intel_psr *psr = &intel_dp->psr;
2252 mutex_lock(&psr->lock);
2254 if (!psr->paused)
2257 psr->paused = false;
2261 mutex_unlock(&psr->lock);
2367 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);
2386 lockdep_assert_held(&intel_dp->psr.lock);
2388 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
2592 intel_dp->psr.panel_replay_enabled &&
2593 intel_dp->psr.sel_update_enabled) {
2823 struct intel_psr *psr = &intel_dp->psr;
2825 mutex_lock(&psr->lock);
2827 if (psr->enabled) {
2839 new_crtc_state->has_sel_update != psr->sel_update_enabled ||
2840 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||
2841 new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||
2849 mutex_unlock(&psr->lock);
2867 struct intel_psr *psr = &intel_dp->psr;
2870 mutex_lock(&psr->lock);
2873 psr->enabled && !crtc_state->active_planes);
2875 keep_disabled |= psr->sink_not_reliable;
2882 if (!psr->enabled && !keep_disabled)
2884 else if (psr->enabled && !crtc_state->wm_level_disabled)
2889 if (crtc_state->crc_enabled && psr->enabled)
2896 intel_dp->psr.busy_frontbuffer_bits = 0;
2898 mutex_unlock(&psr->lock);
2905 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2920 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2953 lockdep_assert_held(&intel_dp->psr.lock);
2955 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
2958 if (intel_dp->psr.sel_update_enabled)
2972 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2977 if (!intel_dp->psr.enabled)
2980 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
2981 intel_dp->psr.panel_replay_enabled)) {
2989 mutex_unlock(&intel_dp->psr.lock);
2997 mutex_lock(&intel_dp->psr.lock);
2998 return err == 0 && intel_dp->psr.enabled;
3081 ret = mutex_lock_interruptible(&intel_dp->psr.lock);
3085 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
3086 old_disable_bits = intel_dp->psr.debug &
3090 intel_dp->psr.debug = val;
3096 if (intel_dp->psr.enabled)
3099 mutex_unlock(&intel_dp->psr.lock);
3109 struct intel_psr *psr = &intel_dp->psr;
3112 psr->sink_not_reliable = true;
3120 container_of(work, typeof(*intel_dp), psr.work);
3122 mutex_lock(&intel_dp->psr.lock);
3124 if (!intel_dp->psr.enabled)
3127 if (READ_ONCE(intel_dp->psr.irq_aux_error))
3144 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
3149 mutex_unlock(&intel_dp->psr.lock);
3155 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3157 if (!intel_dp->psr.psr2_sel_fetch_enabled)
3174 if (intel_dp->psr.psr2_sel_fetch_enabled) {
3175 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3176 intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
3211 mutex_lock(&intel_dp->psr.lock);
3212 if (!intel_dp->psr.enabled) {
3213 mutex_unlock(&intel_dp->psr.lock);
3218 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3219 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
3224 mutex_unlock(&intel_dp->psr.lock);
3240 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
3241 !intel_dp->psr.active)
3249 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
3253 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work,
3254 intel_dp->psr.dc3co_exit_delay);
3262 if (intel_dp->psr.psr2_sel_fetch_enabled) {
3263 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3265 if (intel_dp->psr.busy_frontbuffer_bits == 0)
3266 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
3283 if (!intel_dp->psr.psr2_sel_fetch_enabled && !intel_dp->psr.active &&
3284 !intel_dp->psr.busy_frontbuffer_bits)
3285 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
3310 mutex_lock(&intel_dp->psr.lock);
3311 if (!intel_dp->psr.enabled) {
3312 mutex_unlock(&intel_dp->psr.lock);
3317 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3318 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
3325 if (intel_dp->psr.paused)
3330 !intel_dp->psr.psr2_sel_fetch_enabled)) {
3341 mutex_unlock(&intel_dp->psr.lock);
3379 intel_dp->psr.source_panel_replay_support = true;
3382 intel_dp->psr.source_support = true;
3387 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
3389 INIT_WORK(&intel_dp->psr.work, intel_psr_work);
3390 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
3391 mutex_init(&intel_dp->psr.lock);
3401 offset = intel_dp->psr.panel_replay_enabled ?
3408 offset = intel_dp->psr.panel_replay_enabled ?
3424 struct intel_psr *psr = &intel_dp->psr;
3428 if (!psr->sel_update_enabled)
3439 psr->sink_not_reliable = true;
3451 struct intel_psr *psr = &intel_dp->psr;
3463 psr->sink_not_reliable = true;
3482 struct intel_psr *psr = &intel_dp->psr;
3491 mutex_lock(&psr->lock);
3493 psr->link_ok = false;
3495 if (!psr->enabled)
3504 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||
3507 psr->sink_not_reliable = true;
3510 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&
3531 if (!psr->panel_replay_enabled) {
3537 mutex_unlock(&psr->lock);
3547 mutex_lock(&intel_dp->psr.lock);
3548 ret = intel_dp->psr.enabled;
3549 mutex_unlock(&intel_dp->psr.lock);
3555 * intel_psr_link_ok - return psr->link_ok
3574 mutex_lock(&intel_dp->psr.lock);
3575 ret = intel_dp->psr.link_ok;
3576 mutex_unlock(&intel_dp->psr.lock);
3601 mutex_lock(&intel_dp->psr.lock);
3624 mutex_unlock(&intel_dp->psr.lock);
3633 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3637 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
3638 intel_dp->psr.panel_replay_enabled)) {
3681 struct intel_psr *psr = &intel_dp->psr;
3684 str_yes_no(psr->sink_support));
3686 if (psr->sink_support)
3690 seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
3692 str_yes_no(psr->sink_panel_replay_su_support));
3701 struct intel_psr *psr = &intel_dp->psr;
3704 if (psr->enabled)
3709 if (psr->panel_replay_enabled && psr->sel_update_enabled)
3711 else if (psr->panel_replay_enabled)
3713 else if (psr->sel_update_enabled)
3715 else if (psr->enabled)
3720 if (psr->su_region_et_enabled)
3732 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3733 struct intel_psr *psr = &intel_dp->psr;
3740 if (!(psr->sink_support || psr->sink_panel_replay_support))
3744 mutex_lock(&psr->lock);
3748 if (!psr->enabled) {
3750 str_yes_no(psr->sink_not_reliable));
3755 if (psr->panel_replay_enabled) {
3764 } else if (psr->sel_update_enabled) {
3774 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
3779 psr->busy_frontbuffer_bits);
3788 if (psr->debug & I915_PSR_DEBUG_IRQ) {
3790 psr->last_entry_attempt);
3791 seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
3794 if (psr->sel_update_enabled) {
3820 str_enabled_disabled(psr->psr2_sel_fetch_enabled));
3824 mutex_unlock(&psr->lock);
3893 *val = READ_ONCE(intel_dp->psr.debug);
3917 if (intel_dp->psr.panel_replay_enabled)
3919 else if (intel_dp->psr.enabled)