32 	struct intel_pps *pps = &intel_dp->pps;  in pps_name()  local
35 		switch (pps->vlv_pps_pipe) {  in pps_name()
47 			MISSING_CASE(pps->vlv_pps_pipe);  in pps_name()
51 		switch (pps->pps_idx) {  in pps_name()
57 			MISSING_CASE(pps->pps_idx);  in pps_name()
75 	mutex_lock(&display->pps.mutex);  in intel_pps_lock()
86 	mutex_unlock(&display->pps.mutex);  in intel_pps_unlock()
98 	enum pipe pipe = intel_dp->pps.vlv_pps_pipe;  in vlv_power_sequencer_kick()
184 				    intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&  in vlv_find_free_pps()
185 				    intel_dp->pps.vlv_active_pipe !=  in vlv_find_free_pps()
186 				    intel_dp->pps.vlv_pps_pipe);  in vlv_find_free_pps()
188 			if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)  in vlv_find_free_pps()
189 				pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);  in vlv_find_free_pps()
192 				    intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);  in vlv_find_free_pps()
194 			if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)  in vlv_find_free_pps()
195 				pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);  in vlv_find_free_pps()
212 	lockdep_assert_held(&display->pps.mutex);  in vlv_power_sequencer_pipe()
217 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&  in vlv_power_sequencer_pipe()
218 		    intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);  in vlv_power_sequencer_pipe()
220 	if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)  in vlv_power_sequencer_pipe()
221 		return intel_dp->pps.vlv_pps_pipe;  in vlv_power_sequencer_pipe()
233 	intel_dp->pps.vlv_pps_pipe = pipe;  in vlv_power_sequencer_pipe()
250 	return intel_dp->pps.vlv_pps_pipe;  in vlv_power_sequencer_pipe()
257 	int pps_idx = intel_dp->pps.pps_idx;  in bxt_power_sequencer_idx()
259 	lockdep_assert_held(&display->pps.mutex);  in bxt_power_sequencer_idx()
264 	if (!intel_dp->pps.bxt_pps_reset)  in bxt_power_sequencer_idx()
267 	intel_dp->pps.bxt_pps_reset = false;  in bxt_power_sequencer_idx()
325 	lockdep_assert_held(&display->pps.mutex);  in vlv_initial_power_sequencer_setup()
329 	intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,  in vlv_initial_power_sequencer_setup()
332 	if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)  in vlv_initial_power_sequencer_setup()
333 		intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,  in vlv_initial_power_sequencer_setup()
336 	if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)  in vlv_initial_power_sequencer_setup()
337 		intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,  in vlv_initial_power_sequencer_setup()
341 	if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {  in vlv_initial_power_sequencer_setup()
381 	if (intel_dp->pps.pps_idx == 1 &&  in intel_pps_is_valid()
409 	lockdep_assert_held(&display->pps.mutex);  in pps_initial_setup()
418 		intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;  in pps_initial_setup()
420 		intel_dp->pps.pps_idx = 0;  in pps_initial_setup()
422 	if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))  in pps_initial_setup()
423 		intel_dp->pps.pps_idx = -1;  in pps_initial_setup()
426 	if (intel_dp->pps.pps_idx < 0)  in pps_initial_setup()
427 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);  in pps_initial_setup()
429 	if (intel_dp->pps.pps_idx < 0)  in pps_initial_setup()
430 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);  in pps_initial_setup()
432 	if (intel_dp->pps.pps_idx < 0) {  in pps_initial_setup()
433 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);  in pps_initial_setup()
469 		drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);  in vlv_pps_reset_all()
472 			intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;  in vlv_pps_reset_all()
489 			intel_dp->pps.bxt_pps_reset = true;  in bxt_pps_reset_all()
515 		pps_idx = intel_dp->pps.pps_idx;  in intel_pps_get_registers()
554 	lockdep_assert_held(&display->pps.mutex);  in edp_have_panel_power()
557 	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)  in edp_have_panel_power()
567 	lockdep_assert_held(&display->pps.mutex);  in edp_have_panel_vdd()
570 	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)  in edp_have_panel_vdd()
616 	lockdep_assert_held(&display->pps.mutex);  in wait_panel_status()
681 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);  in wait_panel_power_cycle()
685 	if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)  in wait_panel_power_cycle()
687 				       intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);  in wait_panel_power_cycle()
705 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,  in wait_backlight_on()
706 				       intel_dp->pps.backlight_on_delay);  in wait_backlight_on()
711 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,  in edp_wait_backlight_off()
712 				       intel_dp->pps.backlight_off_delay);  in edp_wait_backlight_off()
724 	lockdep_assert_held(&display->pps.mutex);  in ilk_get_pp_control()
747 	bool need_to_disable = !intel_dp->pps.want_panel_vdd;  in intel_pps_vdd_on_unlocked()
749 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_vdd_on_unlocked()
754 	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);  in intel_pps_vdd_on_unlocked()
755 	intel_dp->pps.want_panel_vdd = true;  in intel_pps_vdd_on_unlocked()
760 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);  in intel_pps_vdd_on_unlocked()
761 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,  in intel_pps_vdd_on_unlocked()
793 		msleep(intel_dp->pps.panel_power_up_delay);  in intel_pps_vdd_on_unlocked()
832 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_vdd_off_sync_unlocked()
834 	drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);  in intel_pps_vdd_off_sync_unlocked()
861 		intel_dp->pps.panel_power_off_time = ktime_get_boottime();  in intel_pps_vdd_off_sync_unlocked()
867 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));  in intel_pps_vdd_off_sync_unlocked()
877 	cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);  in intel_pps_vdd_off_sync()
888 	struct intel_pps *pps = container_of(to_delayed_work(__work),  in edp_panel_vdd_work()  local
890 	struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);  in edp_panel_vdd_work()
894 		if (!intel_dp->pps.want_panel_vdd)  in edp_panel_vdd_work()
909 	if (intel_dp->pps.initializing)  in edp_panel_vdd_schedule_off()
917 	delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);  in edp_panel_vdd_schedule_off()
919 			   &intel_dp->pps.panel_vdd_work, delay);  in edp_panel_vdd_schedule_off()
931 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_vdd_off_unlocked()
936 	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,  in intel_pps_vdd_off_unlocked()
942 	intel_dp->pps.want_panel_vdd = false;  in intel_pps_vdd_off_unlocked()
967 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_on_unlocked()
1011 	intel_dp->pps.last_power_on = jiffies;  in intel_pps_on_unlocked()
1043 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_off_unlocked()
1052 	drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,  in intel_pps_off_unlocked()
1065 	intel_dp->pps.want_panel_vdd = false;  in intel_pps_off_unlocked()
1071 	intel_dp->pps.panel_power_off_time = ktime_get_boottime();  in intel_pps_off_unlocked()
1078 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));  in intel_pps_off_unlocked()
1138 	intel_dp->pps.last_backlight_off = jiffies;  in intel_pps_backlight_off()
1172 	enum pipe pipe = intel_dp->pps.vlv_pps_pipe;  in vlv_detach_power_sequencer()
1175 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);  in vlv_detach_power_sequencer()
1198 	intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;  in vlv_detach_power_sequencer()
1206 	lockdep_assert_held(&display->pps.mutex);  in vlv_steal_power_sequencer()
1211 		drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,  in vlv_steal_power_sequencer()
1216 		if (intel_dp->pps.vlv_pps_pipe != pipe)  in vlv_steal_power_sequencer()
1246 	intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;  in vlv_pps_pipe_init()
1247 	intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);  in vlv_pps_pipe_init()
1256 		intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);  in vlv_pps_pipe_reset()
1271 		pipe = intel_dp->pps.vlv_pps_pipe;  in vlv_pps_backlight_initial_pipe()
1287 	lockdep_assert_held(&display->pps.mutex);  in vlv_pps_port_enable_unlocked()
1289 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);  in vlv_pps_port_enable_unlocked()
1291 	if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&  in vlv_pps_port_enable_unlocked()
1292 	    intel_dp->pps.vlv_pps_pipe != crtc->pipe) {  in vlv_pps_port_enable_unlocked()
1307 	intel_dp->pps.vlv_active_pipe = crtc->pipe;  in vlv_pps_port_enable_unlocked()
1313 	intel_dp->pps.vlv_pps_pipe = crtc->pipe;  in vlv_pps_port_enable_unlocked()
1334 		intel_dp->pps.vlv_active_pipe = INVALID_PIPE;  in vlv_pps_port_disable()
1343 	lockdep_assert_held(&display->pps.mutex);  in pps_vdd_init()
1358 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);  in pps_vdd_init()
1359 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,  in pps_vdd_init()
1384 	intel_dp->pps.panel_power_off_time = 0;  in pps_init_timestamps()
1385 	intel_dp->pps.last_power_on = jiffies;  in pps_init_timestamps()
1386 	intel_dp->pps.last_backlight_off = jiffies;  in pps_init_timestamps()
1441 	struct edp_power_seq *sw = &intel_dp->pps.pps_delays;  in intel_pps_verify_state()
1464 	lockdep_assert_held(&display->pps.mutex);  in pps_init_delays_bios()
1466 	if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))  in pps_init_delays_bios()
1467 		intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);  in pps_init_delays_bios()
1469 	*bios = intel_dp->pps.bios_pps_delays;  in pps_init_delays_bios()
1480 	*vbt = connector->panel.vbt.edp.pps;  in pps_init_delays_vbt()
1511 	lockdep_assert_held(&display->pps.mutex);  in pps_init_delays_spec()
1532 		*final = &intel_dp->pps.pps_delays;  in pps_init_delays()
1534 	lockdep_assert_held(&display->pps.mutex);  in pps_init_delays()
1557 	intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);  in pps_init_delays()
1558 	intel_dp->pps.backlight_on_delay = get_delay(t8);  in pps_init_delays()
1559 	intel_dp->pps.backlight_off_delay = get_delay(t9);  in pps_init_delays()
1560 	intel_dp->pps.panel_power_down_delay = get_delay(t10);  in pps_init_delays()
1561 	intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);  in pps_init_delays()
1566 		    intel_dp->pps.panel_power_up_delay,  in pps_init_delays()
1567 		    intel_dp->pps.panel_power_down_delay,  in pps_init_delays()
1568 		    intel_dp->pps.panel_power_cycle_delay);  in pps_init_delays()
1571 		    intel_dp->pps.backlight_on_delay,  in pps_init_delays()
1572 		    intel_dp->pps.backlight_off_delay);  in pps_init_delays()
1599 	const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;  in pps_init_registers()
1601 	lockdep_assert_held(&display->pps.mutex);  in pps_init_registers()
1713 	intel_dp->pps.initializing = true;  in intel_pps_init()
1714 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);  in intel_pps_init()
1743 		 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,  in pps_init_late()
1746 		 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);  in pps_init_late()
1749 		intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;  in pps_init_late()
1760 		memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));  in intel_pps_init_late()
1764 		intel_dp->pps.initializing = false;  in intel_pps_init_late()
1794 		display->pps.mmio_base = PCH_PPS_BASE;  in intel_pps_setup()
1796 		display->pps.mmio_base = VLV_PPS_BASE;  in intel_pps_setup()
1798 		display->pps.mmio_base = PPS_BASE;  in intel_pps_setup()
1810 		   intel_dp->pps.panel_power_up_delay);  in intel_pps_show()
1812 		   intel_dp->pps.panel_power_down_delay);  in intel_pps_show()
1814 		   intel_dp->pps.backlight_on_delay);  in intel_pps_show()
1816 		   intel_dp->pps.backlight_off_delay);  in intel_pps_show()