Lines Matching +full:pps +full:- +full:channel
1 // SPDX-License-Identifier: MIT
32 struct intel_pps *pps = &intel_dp->pps;
34 if (display->platform.valleyview || display->platform.cherryview) {
35 switch (pps->vlv_pps_pipe) {
39 * to always have a valid PPS when calling this.
41 return "PPS <none>";
43 return "PPS A";
45 return "PPS B";
47 MISSING_CASE(pps->vlv_pps_pipe);
51 switch (pps->pps_idx) {
53 return "PPS 0";
55 return "PPS 1";
57 MISSING_CASE(pps->pps_idx);
62 return "PPS <invalid>";
74 mutex_lock(&display->pps.mutex);
84 mutex_unlock(&display->pps.mutex);
94 struct drm_i915_private *dev_priv = to_i915(display->drm);
96 enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
102 if (drm_WARN(display->drm,
103 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,
106 dig_port->base.base.base.id, dig_port->base.base.name))
109 drm_dbg_kms(display->drm,
112 dig_port->base.base.base.id, dig_port->base.base.name);
114 /* Preserve the BIOS-computed detected bit. This is
115 * supposed to be read-only.
117 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
122 if (display->platform.cherryview)
134 release_cl_override = display->platform.cherryview &&
138 drm_err(display->drm,
151 intel_de_write(display, intel_dp->output_reg, DP);
152 intel_de_posting_read(display, intel_dp->output_reg);
154 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);
155 intel_de_posting_read(display, intel_dp->output_reg);
157 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);
158 intel_de_posting_read(display, intel_dp->output_reg);
177 for_each_intel_dp(display->drm, encoder) {
180 if (encoder->type == INTEL_OUTPUT_EDP) {
181 drm_WARN_ON(display->drm,
182 intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
183 intel_dp->pps.vlv_active_pipe !=
184 intel_dp->pps.vlv_pps_pipe);
186 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)
187 pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);
189 drm_WARN_ON(display->drm,
190 intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);
192 if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)
193 pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);
200 return ffs(pipes) - 1;
210 lockdep_assert_held(&display->pps.mutex);
213 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
215 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
216 intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);
218 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)
219 return intel_dp->pps.vlv_pps_pipe;
227 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))
231 intel_dp->pps.vlv_pps_pipe = pipe;
233 drm_dbg_kms(display->drm,
236 dig_port->base.base.base.id, dig_port->base.base.name);
248 return intel_dp->pps.vlv_pps_pipe;
255 int pps_idx = intel_dp->pps.pps_idx;
257 lockdep_assert_held(&display->pps.mutex);
260 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
262 if (!intel_dp->pps.bxt_pps_reset)
265 intel_dp->pps.bxt_pps_reset = false;
321 enum port port = dig_port->base.port;
323 lockdep_assert_held(&display->pps.mutex);
327 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
330 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
331 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
334 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
335 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
339 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {
340 drm_dbg_kms(display->drm,
342 dig_port->base.base.base.id, dig_port->base.base.name);
346 drm_dbg_kms(display->drm,
348 dig_port->base.base.base.id, dig_port->base.base.name,
354 struct drm_i915_private *i915 = to_i915(display->drm);
356 if (display->platform.valleyview || display->platform.cherryview)
359 if (display->platform.geminilake || display->platform.broxton)
377 struct drm_i915_private *i915 = to_i915(display->drm);
379 if (intel_dp->pps.pps_idx == 1 &&
397 return -1;
404 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
405 struct intel_connector *connector = intel_dp->attached_connector;
407 lockdep_assert_held(&display->pps.mutex);
409 if (display->platform.valleyview || display->platform.cherryview) {
416 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
418 intel_dp->pps.pps_idx = 0;
420 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))
421 intel_dp->pps.pps_idx = -1;
424 if (intel_dp->pps.pps_idx < 0)
425 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);
427 if (intel_dp->pps.pps_idx < 0)
428 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);
430 if (intel_dp->pps.pps_idx < 0) {
431 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);
433 drm_dbg_kms(display->drm,
435 encoder->base.base.id, encoder->base.name,
438 drm_dbg_kms(display->drm,
440 encoder->base.base.id, encoder->base.name,
464 for_each_intel_dp(display->drm, encoder) {
467 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
469 if (encoder->type == INTEL_OUTPUT_EDP)
470 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
483 for_each_intel_dp(display->drm, encoder) {
486 if (encoder->type == INTEL_OUTPUT_EDP)
487 intel_dp->pps.bxt_pps_reset = true;
503 struct drm_i915_private *dev_priv = to_i915(display->drm);
508 if (display->platform.valleyview || display->platform.cherryview)
510 else if (display->platform.geminilake || display->platform.broxton)
513 pps_idx = intel_dp->pps.pps_idx;
515 regs->pp_ctrl = PP_CONTROL(display, pps_idx);
516 regs->pp_stat = PP_STATUS(display, pps_idx);
517 regs->pp_on = PP_ON_DELAYS(display, pps_idx);
518 regs->pp_off = PP_OFF_DELAYS(display, pps_idx);
521 if (display->platform.geminilake || display->platform.broxton ||
523 regs->pp_div = INVALID_MMIO_REG;
525 regs->pp_div = PP_DIVISOR(display, pps_idx);
552 lockdep_assert_held(&display->pps.mutex);
554 if ((display->platform.valleyview || display->platform.cherryview) &&
555 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
565 lockdep_assert_held(&display->pps.mutex);
567 if ((display->platform.valleyview || display->platform.cherryview) &&
568 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
583 drm_WARN(display->drm, 1,
585 dig_port->base.base.base.id, dig_port->base.base.name,
587 drm_dbg_kms(display->drm,
589 dig_port->base.base.base.id, dig_port->base.base.name,
614 lockdep_assert_held(&display->pps.mutex);
621 drm_dbg_kms(display->drm,
623 dig_port->base.base.base.id, dig_port->base.base.name,
630 drm_err(display->drm,
632 dig_port->base.base.base.id, dig_port->base.base.name,
637 drm_dbg_kms(display->drm, "Wait complete\n");
645 drm_dbg_kms(display->drm,
647 dig_port->base.base.base.id, dig_port->base.base.name,
657 drm_dbg_kms(display->drm,
659 dig_port->base.base.base.id, dig_port->base.base.name,
674 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
676 remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
678 drm_dbg_kms(display->drm,
680 dig_port->base.base.base.id, dig_port->base.base.name,
704 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
705 intel_dp->pps.backlight_on_delay);
710 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
711 intel_dp->pps.backlight_off_delay);
723 lockdep_assert_held(&display->pps.mutex);
726 if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&
745 bool need_to_disable = !intel_dp->pps.want_panel_vdd;
747 lockdep_assert_held(&display->pps.mutex);
752 cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
753 intel_dp->pps.want_panel_vdd = true;
758 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
759 intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
765 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
766 dig_port->base.base.base.id, dig_port->base.base.name,
777 drm_dbg_kms(display->drm,
779 dig_port->base.base.base.id, dig_port->base.base.name,
784 * If the panel wasn't on, delay before accessing aux channel
787 drm_dbg_kms(display->drm,
789 dig_port->base.base.base.id, dig_port->base.base.name,
791 msleep(intel_dp->pps.panel_power_up_delay);
798 * Must be paired with intel_pps_vdd_off() or - to disable
799 * both VDD and panel power - intel_pps_off().
817 dp_to_dig_port(intel_dp)->base.base.base.id,
818 dp_to_dig_port(intel_dp)->base.base.name,
829 lockdep_assert_held(&display->pps.mutex);
831 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);
836 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
837 dig_port->base.base.base.id, dig_port->base.base.name,
850 drm_dbg_kms(display->drm,
852 dig_port->base.base.base.id, dig_port->base.base.name,
858 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
864 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
874 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
885 struct intel_pps *pps = container_of(to_delayed_work(__work),
887 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
891 if (!intel_dp->pps.want_panel_vdd)
899 struct drm_i915_private *i915 = to_i915(display->drm);
906 if (intel_dp->pps.initializing)
914 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
915 queue_delayed_work(i915->unordered_wq,
916 &intel_dp->pps.panel_vdd_work, delay);
928 lockdep_assert_held(&display->pps.mutex);
933 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
935 dp_to_dig_port(intel_dp)->base.base.base.id,
936 dp_to_dig_port(intel_dp)->base.base.name,
939 intel_dp->pps.want_panel_vdd = false;
964 lockdep_assert_held(&display->pps.mutex);
969 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
970 dp_to_dig_port(intel_dp)->base.base.base.id,
971 dp_to_dig_port(intel_dp)->base.base.name,
974 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),
976 dp_to_dig_port(intel_dp)->base.base.base.id,
977 dp_to_dig_port(intel_dp)->base.base.name,
985 if (display->platform.ironlake) {
1001 if (!display->platform.ironlake)
1008 intel_dp->pps.last_power_on = jiffies;
1014 if (display->platform.ironlake) {
1039 lockdep_assert_held(&display->pps.mutex);
1044 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
1045 dig_port->base.base.base.id, dig_port->base.base.name,
1048 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,
1050 dig_port->base.base.base.id, dig_port->base.base.name,
1061 intel_dp->pps.want_panel_vdd = false;
1067 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1074 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
1134 intel_dp->pps.last_backlight_off = jiffies;
1155 drm_dbg_kms(display->drm, "panel power control backlight %s\n",
1168 enum pipe pipe = intel_dp->pps.vlv_pps_pipe;
1171 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1173 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
1187 drm_dbg_kms(display->drm,
1190 dig_port->base.base.base.id, dig_port->base.base.name);
1194 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
1202 lockdep_assert_held(&display->pps.mutex);
1204 for_each_intel_dp(display->drm, encoder) {
1207 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,
1208 "stealing PPS %c from active [ENCODER:%d:%s]\n",
1209 pipe_name(pipe), encoder->base.base.id,
1210 encoder->base.name);
1212 if (intel_dp->pps.vlv_pps_pipe != pipe)
1215 drm_dbg_kms(display->drm,
1216 "stealing PPS %c from [ENCODER:%d:%s]\n",
1217 pipe_name(pipe), encoder->base.base.id,
1218 encoder->base.name);
1228 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1231 if (g4x_dp_port_enabled(display, intel_dp->output_reg,
1232 encoder->port, &pipe))
1241 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
1242 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
1251 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);
1260 * current pipe isn't valid, try the PPS pipe, and if that fails just
1266 pipe = intel_dp->pps.vlv_pps_pipe;
1280 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1282 lockdep_assert_held(&display->pps.mutex);
1284 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1286 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&
1287 intel_dp->pps.vlv_pps_pipe != crtc->pipe) {
1300 vlv_steal_power_sequencer(display, crtc->pipe);
1302 intel_dp->pps.vlv_active_pipe = crtc->pipe;
1308 intel_dp->pps.vlv_pps_pipe = crtc->pipe;
1310 drm_dbg_kms(display->drm,
1313 encoder->base.base.id, encoder->base.name);
1329 intel_dp->pps.vlv_active_pipe = INVALID_PIPE;
1337 lockdep_assert_held(&display->pps.mutex);
1348 drm_dbg_kms(display->drm,
1350 dig_port->base.base.base.id, dig_port->base.base.name,
1352 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
1353 intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
1378 intel_dp->pps.panel_power_off_time = 0;
1379 intel_dp->pps.last_power_on = jiffies;
1380 intel_dp->pps.last_backlight_off = jiffies;
1394 /* Ensure PPS is unlocked */
1402 seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1403 seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1404 seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1405 seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1418 seq->power_cycle = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0;
1427 drm_dbg_kms(display->drm,
1429 state_name, seq->power_up, seq->backlight_on,
1430 seq->backlight_off, seq->power_down, seq->power_cycle);
1438 struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;
1442 if (hw.power_up != sw->power_up ||
1443 hw.backlight_on != sw->backlight_on ||
1444 hw.backlight_off != sw->backlight_off ||
1445 hw.power_down != sw->power_down ||
1446 hw.power_cycle != sw->power_cycle) {
1447 drm_err(display->drm, "PPS state mismatch\n");
1455 return delays->power_up || delays->backlight_on || delays->backlight_off ||
1456 delays->power_down || delays->power_cycle;
1461 /* PPS uses 100us units */
1467 /* PPS uses 100us units */
1476 lockdep_assert_held(&display->pps.mutex);
1478 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
1479 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
1481 *bios = intel_dp->pps.bios_pps_delays;
1490 struct intel_connector *connector = intel_dp->attached_connector;
1492 *vbt = connector->panel.vbt.edp.pps;
1498 * On Toshiba Satellite P50-C-18C system the VBT T12 delay
1504 vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300));
1505 drm_dbg_kms(display->drm,
1507 vbt->power_cycle);
1518 lockdep_assert_held(&display->pps.mutex);
1521 spec->power_up = msecs_to_pps_units(10 + 200); /* T1+T3 */
1522 spec->backlight_on = msecs_to_pps_units(50); /* no limit for T8, use T7 instead */
1523 spec->backlight_off = msecs_to_pps_units(50); /* no limit for T9, make it symmetric with T8 */
1524 spec->power_down = msecs_to_pps_units(500); /* T10 */
1525 spec->power_cycle = msecs_to_pps_units(10 + 500); /* T11+T12 */
1534 *final = &intel_dp->pps.pps_delays;
1536 lockdep_assert_held(&display->pps.mutex);
1548 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
1558 intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);
1559 intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);
1560 intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);
1561 intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);
1562 intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);
1564 drm_dbg_kms(display->drm,
1566 intel_dp->pps.panel_power_up_delay,
1567 intel_dp->pps.panel_power_down_delay,
1568 intel_dp->pps.panel_power_cycle_delay);
1570 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",
1571 intel_dp->pps.backlight_on_delay,
1572 intel_dp->pps.backlight_off_delay);
1582 final->backlight_on = 1;
1583 final->backlight_off = 1;
1589 final->power_cycle = roundup(final->power_cycle, msecs_to_pps_units(100));
1595 struct drm_i915_private *dev_priv = to_i915(display->drm);
1597 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;
1599 enum port port = dp_to_dig_port(intel_dp)->base.port;
1600 const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;
1602 lockdep_assert_held(&display->pps.mutex);
1621 drm_WARN(display->drm, pp & PANEL_POWER_ON,
1625 drm_dbg_kms(display->drm,
1633 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) |
1634 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on);
1635 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) |
1636 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down);
1640 if (display->platform.valleyview || display->platform.cherryview) {
1670 (100 * div) / 2 - 1) |
1672 DIV_ROUND_UP(seq->power_cycle, 1000) + 1));
1676 DIV_ROUND_UP(seq->power_cycle, 1000) + 1));
1678 drm_dbg_kms(display->drm,
1700 if (display->platform.valleyview || display->platform.cherryview)
1717 intel_dp->pps.initializing = true;
1718 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1736 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1737 struct intel_connector *connector = intel_dp->attached_connector;
1739 if (display->platform.valleyview || display->platform.cherryview)
1745 drm_WARN(display->drm,
1746 connector->panel.vbt.backlight.controller >= 0 &&
1747 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,
1749 encoder->base.base.id, encoder->base.name,
1750 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);
1752 if (connector->panel.vbt.backlight.controller >= 0)
1753 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
1761 /* Reinit delays after per-panel info has been parsed from VBT */
1764 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
1768 intel_dp->pps.initializing = false;
1795 struct drm_i915_private *i915 = to_i915(display->drm);
1797 if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton)
1798 display->pps.mmio_base = PCH_PPS_BASE;
1799 else if (display->platform.valleyview || display->platform.cherryview)
1800 display->pps.mmio_base = VLV_PPS_BASE;
1802 display->pps.mmio_base = PPS_BASE;
1807 struct intel_connector *connector = m->private;
1810 if (connector->base.status != connector_status_connected)
1811 return -ENODEV;
1814 intel_dp->pps.panel_power_up_delay);
1816 intel_dp->pps.panel_power_down_delay);
1818 intel_dp->pps.panel_power_cycle_delay);
1820 intel_dp->pps.backlight_on_delay);
1822 intel_dp->pps.backlight_off_delay);
1830 struct dentry *root = connector->base.debugfs_entry;
1831 int connector_type = connector->base.connector_type;
1840 struct drm_i915_private *dev_priv = to_i915(display->drm);
1846 if (drm_WARN_ON(display->drm, HAS_DDI(display)))
1873 } else if (display->platform.valleyview || display->platform.cherryview) {
1884 drm_WARN_ON(display->drm,