Lines Matching defs:display
23 static void vlv_steal_power_sequencer(struct intel_display *display,
31 struct intel_display *display = to_intel_display(intel_dp);
34 if (display->platform.valleyview || display->platform.cherryview) {
67 struct intel_display *display = to_intel_display(intel_dp);
73 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
74 mutex_lock(&display->pps.mutex);
82 struct intel_display *display = to_intel_display(intel_dp);
84 mutex_unlock(&display->pps.mutex);
85 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
93 struct intel_display *display = to_intel_display(intel_dp);
94 struct drm_i915_private *dev_priv = to_i915(display->drm);
102 if (drm_WARN(display->drm,
103 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,
109 drm_dbg_kms(display->drm,
117 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
122 if (display->platform.cherryview)
127 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
134 release_cl_override = display->platform.cherryview &&
135 !chv_phy_powergate_ch(display, phy, ch, true);
137 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) {
138 drm_err(display->drm,
151 intel_de_write(display, intel_dp->output_reg, DP);
152 intel_de_posting_read(display, intel_dp->output_reg);
154 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);
155 intel_de_posting_read(display, intel_dp->output_reg);
157 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);
158 intel_de_posting_read(display, intel_dp->output_reg);
164 chv_phy_powergate_ch(display, phy, ch, false);
168 static enum pipe vlv_find_free_pps(struct intel_display *display)
177 for_each_intel_dp(display->drm, encoder) {
181 drm_WARN_ON(display->drm,
189 drm_WARN_ON(display->drm,
206 struct intel_display *display = to_intel_display(intel_dp);
210 lockdep_assert_held(&display->pps.mutex);
213 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
215 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&
221 pipe = vlv_find_free_pps(display);
227 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))
230 vlv_steal_power_sequencer(display, pipe);
233 drm_dbg_kms(display->drm,
254 struct intel_display *display = to_intel_display(intel_dp);
257 lockdep_assert_held(&display->pps.mutex);
260 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
276 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
278 static bool pps_has_pp_on(struct intel_display *display, int pps_idx)
280 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;
283 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)
285 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;
288 static bool pps_any(struct intel_display *display, int pps_idx)
294 vlv_initial_pps_pipe(struct intel_display *display,
300 u32 port_sel = intel_de_read(display,
301 PP_ON_DELAYS(display, pipe)) &
307 if (!check(display, pipe))
319 struct intel_display *display = to_intel_display(intel_dp);
323 lockdep_assert_held(&display->pps.mutex);
327 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
331 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
335 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,
340 drm_dbg_kms(display->drm,
346 drm_dbg_kms(display->drm,
352 static int intel_num_pps(struct intel_display *display)
354 struct drm_i915_private *i915 = to_i915(display->drm);
356 if (display->platform.valleyview || display->platform.cherryview)
359 if (display->platform.geminilake || display->platform.broxton)
376 struct intel_display *display = to_intel_display(intel_dp);
377 struct drm_i915_private *i915 = to_i915(display->drm);
382 return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
388 bxt_initial_pps_idx(struct intel_display *display, pps_check check)
390 int pps_idx, pps_num = intel_num_pps(display);
393 if (check(display, pps_idx))
403 struct intel_display *display = to_intel_display(intel_dp);
407 lockdep_assert_held(&display->pps.mutex);
409 if (display->platform.valleyview || display->platform.cherryview) {
415 if (intel_num_pps(display) > 1)
420 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))
425 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);
428 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);
431 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);
433 drm_dbg_kms(display->drm,
438 drm_dbg_kms(display->drm,
447 void vlv_pps_reset_all(struct intel_display *display)
451 if (!HAS_DISPLAY(display))
464 for_each_intel_dp(display->drm, encoder) {
467 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
474 void bxt_pps_reset_all(struct intel_display *display)
478 if (!HAS_DISPLAY(display))
483 for_each_intel_dp(display->drm, encoder) {
502 struct intel_display *display = to_intel_display(intel_dp);
503 struct drm_i915_private *dev_priv = to_i915(display->drm);
508 if (display->platform.valleyview || display->platform.cherryview)
510 else if (display->platform.geminilake || display->platform.broxton)
515 regs->pp_ctrl = PP_CONTROL(display, pps_idx);
516 regs->pp_stat = PP_STATUS(display, pps_idx);
517 regs->pp_on = PP_ON_DELAYS(display, pps_idx);
518 regs->pp_off = PP_OFF_DELAYS(display, pps_idx);
521 if (display->platform.geminilake || display->platform.broxton ||
525 regs->pp_div = PP_DIVISOR(display, pps_idx);
550 struct intel_display *display = to_intel_display(intel_dp);
552 lockdep_assert_held(&display->pps.mutex);
554 if ((display->platform.valleyview || display->platform.cherryview) &&
558 return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
563 struct intel_display *display = to_intel_display(intel_dp);
565 lockdep_assert_held(&display->pps.mutex);
567 if ((display->platform.valleyview || display->platform.cherryview) &&
571 return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
576 struct intel_display *display = to_intel_display(intel_dp);
583 drm_WARN(display->drm, 1,
587 drm_dbg_kms(display->drm,
591 intel_de_read(display, _pp_stat_reg(intel_dp)),
592 intel_de_read(display, _pp_ctrl_reg(intel_dp)));
610 struct intel_display *display = to_intel_display(intel_dp);
614 lockdep_assert_held(&display->pps.mutex);
621 drm_dbg_kms(display->drm,
626 intel_de_read(display, pp_stat_reg),
627 intel_de_read(display, pp_ctrl_reg));
629 if (intel_de_wait(display, pp_stat_reg, mask, value, 5000))
630 drm_err(display->drm,
634 intel_de_read(display, pp_stat_reg),
635 intel_de_read(display, pp_ctrl_reg));
637 drm_dbg_kms(display->drm, "Wait complete\n");
642 struct intel_display *display = to_intel_display(intel_dp);
645 drm_dbg_kms(display->drm,
654 struct intel_display *display = to_intel_display(intel_dp);
657 drm_dbg_kms(display->drm,
666 struct intel_display *display = to_intel_display(intel_dp);
678 drm_dbg_kms(display->drm,
720 struct intel_display *display = to_intel_display(intel_dp);
723 lockdep_assert_held(&display->pps.mutex);
725 control = intel_de_read(display, _pp_ctrl_reg(intel_dp));
726 if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&
741 struct intel_display *display = to_intel_display(intel_dp);
747 lockdep_assert_held(&display->pps.mutex);
758 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
759 intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
765 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
775 intel_de_write(display, pp_ctrl_reg, pp);
776 intel_de_posting_read(display, pp_ctrl_reg);
777 drm_dbg_kms(display->drm,
781 intel_de_read(display, pp_stat_reg),
782 intel_de_read(display, pp_ctrl_reg));
787 drm_dbg_kms(display->drm,
806 struct intel_display *display = to_intel_display(intel_dp);
816 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
824 struct intel_display *display = to_intel_display(intel_dp);
829 lockdep_assert_held(&display->pps.mutex);
831 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);
836 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
846 intel_de_write(display, pp_ctrl_reg, pp);
847 intel_de_posting_read(display, pp_ctrl_reg);
850 drm_dbg_kms(display->drm,
854 intel_de_read(display, pp_stat_reg),
855 intel_de_read(display, pp_ctrl_reg));
862 intel_display_power_put(display,
898 struct intel_display *display = to_intel_display(intel_dp);
899 struct drm_i915_private *i915 = to_i915(display->drm);
926 struct intel_display *display = to_intel_display(intel_dp);
928 lockdep_assert_held(&display->pps.mutex);
933 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
960 struct intel_display *display = to_intel_display(intel_dp);
964 lockdep_assert_held(&display->pps.mutex);
969 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
974 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),
985 if (display->platform.ironlake) {
988 intel_de_write(display, pp_ctrl_reg, pp);
989 intel_de_posting_read(display, pp_ctrl_reg);
996 if (IS_DISPLAY_VER(display, 13, 14))
997 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1001 if (!display->platform.ironlake)
1004 intel_de_write(display, pp_ctrl_reg, pp);
1005 intel_de_posting_read(display, pp_ctrl_reg);
1010 if (IS_DISPLAY_VER(display, 13, 14))
1011 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1014 if (display->platform.ironlake) {
1016 intel_de_write(display, pp_ctrl_reg, pp);
1017 intel_de_posting_read(display, pp_ctrl_reg);
1034 struct intel_display *display = to_intel_display(intel_dp);
1039 lockdep_assert_held(&display->pps.mutex);
1044 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
1048 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,
1063 intel_de_write(display, pp_ctrl_reg, pp);
1064 intel_de_posting_read(display, pp_ctrl_reg);
1072 intel_display_power_put(display,
1091 struct intel_display *display = to_intel_display(intel_dp);
1109 intel_de_write(display, pp_ctrl_reg, pp);
1110 intel_de_posting_read(display, pp_ctrl_reg);
1117 struct intel_display *display = to_intel_display(intel_dp);
1130 intel_de_write(display, pp_ctrl_reg, pp);
1131 intel_de_posting_read(display, pp_ctrl_reg);
1144 struct intel_display *display = to_intel_display(connector);
1155 drm_dbg_kms(display->drm, "panel power control backlight %s\n",
1166 struct intel_display *display = to_intel_display(intel_dp);
1169 i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
1171 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1173 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))
1187 drm_dbg_kms(display->drm,
1191 intel_de_write(display, pp_on_reg, 0);
1192 intel_de_posting_read(display, pp_on_reg);
1197 static void vlv_steal_power_sequencer(struct intel_display *display,
1202 lockdep_assert_held(&display->pps.mutex);
1204 for_each_intel_dp(display->drm, encoder) {
1207 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,
1215 drm_dbg_kms(display->drm,
1227 struct intel_display *display = to_intel_display(intel_dp);
1231 if (g4x_dp_port_enabled(display, intel_dp->output_reg,
1278 struct intel_display *display = to_intel_display(encoder);
1282 lockdep_assert_held(&display->pps.mutex);
1284 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);
1300 vlv_steal_power_sequencer(display, crtc->pipe);
1310 drm_dbg_kms(display->drm,
1334 struct intel_display *display = to_intel_display(intel_dp);
1337 lockdep_assert_held(&display->pps.mutex);
1348 drm_dbg_kms(display->drm,
1352 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
1353 intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
1386 struct intel_display *display = to_intel_display(intel_dp);
1395 if (!HAS_DDI(display))
1396 intel_de_write(display, regs.pp_ctrl, pp_ctl);
1398 pp_on = intel_de_read(display, regs.pp_on);
1399 pp_off = intel_de_read(display, regs.pp_off);
1410 pp_div = intel_de_read(display, regs.pp_div);
1425 struct intel_display *display = to_intel_display(intel_dp);
1427 drm_dbg_kms(display->drm,
1436 struct intel_display *display = to_intel_display(intel_dp);
1447 drm_err(display->drm, "PPS state mismatch\n");
1474 struct intel_display *display = to_intel_display(intel_dp);
1476 lockdep_assert_held(&display->pps.mutex);
1489 struct intel_display *display = to_intel_display(intel_dp);
1503 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {
1505 drm_dbg_kms(display->drm,
1516 struct intel_display *display = to_intel_display(intel_dp);
1518 lockdep_assert_held(&display->pps.mutex);
1532 struct intel_display *display = to_intel_display(intel_dp);
1536 lockdep_assert_held(&display->pps.mutex);
1564 drm_dbg_kms(display->drm,
1570 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",
1594 struct intel_display *display = to_intel_display(intel_dp);
1595 struct drm_i915_private *dev_priv = to_i915(display->drm);
1597 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;
1602 lockdep_assert_held(&display->pps.mutex);
1621 drm_WARN(display->drm, pp & PANEL_POWER_ON,
1625 drm_dbg_kms(display->drm,
1630 intel_de_write(display, regs.pp_ctrl, pp);
1640 if (display->platform.valleyview || display->platform.cherryview) {
1661 intel_de_write(display, regs.pp_on, pp_on);
1662 intel_de_write(display, regs.pp_off, pp_off);
1668 intel_de_write(display, regs.pp_div,
1674 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
1678 drm_dbg_kms(display->drm,
1680 intel_de_read(display, regs.pp_on),
1681 intel_de_read(display, regs.pp_off),
1683 intel_de_read(display, regs.pp_div) :
1684 (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1689 struct intel_display *display = to_intel_display(intel_dp);
1700 if (display->platform.valleyview || display->platform.cherryview)
1735 struct intel_display *display = to_intel_display(intel_dp);
1739 if (display->platform.valleyview || display->platform.cherryview)
1742 if (intel_num_pps(display) < 2)
1745 drm_WARN(display->drm,
1775 void intel_pps_unlock_regs_wa(struct intel_display *display)
1780 if (!HAS_DISPLAY(display) || HAS_DDI(display))
1786 pps_num = intel_num_pps(display);
1789 intel_de_rmw(display, PP_CONTROL(display, pps_idx),
1793 void intel_pps_setup(struct intel_display *display)
1795 struct drm_i915_private *i915 = to_i915(display->drm);
1797 if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton)
1798 display->pps.mmio_base = PCH_PPS_BASE;
1799 else if (display->platform.valleyview || display->platform.cherryview)
1800 display->pps.mmio_base = VLV_PPS_BASE;
1802 display->pps.mmio_base = PPS_BASE;
1838 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
1840 struct drm_i915_private *dev_priv = to_i915(display->drm);
1846 if (drm_WARN_ON(display->drm, HAS_DDI(display)))
1852 pp_reg = PP_CONTROL(display, 0);
1853 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
1861 g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);
1864 g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);
1867 g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);
1873 } else if (display->platform.valleyview || display->platform.cherryview) {
1875 pp_reg = PP_CONTROL(display, pipe);
1880 pp_reg = PP_CONTROL(display, 0);
1881 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &
1884 drm_WARN_ON(display->drm,
1889 val = intel_de_read(display, pp_reg);
1894 INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,