Lines Matching +full:de +full:- +full:serialized
1 // SPDX-License-Identifier: MIT
24 u8 active_dbufs; /* pre-Xe3 only */
31 u8 scalers; /* pre-Xe3 only */
57 pmdemand_state = kmemdup(obj->state, sizeof(*pmdemand_state), GFP_KERNEL); in intel_pmdemand_duplicate_state()
61 return &pmdemand_state->base; in intel_pmdemand_duplicate_state()
81 &display->pmdemand.obj); in intel_atomic_get_pmdemand_state()
95 &display->pmdemand.obj); in intel_atomic_get_old_pmdemand_state()
109 &display->pmdemand.obj); in intel_atomic_get_new_pmdemand_state()
123 return -ENOMEM; in intel_pmdemand_init()
125 intel_atomic_global_obj_init(display, &display->pmdemand.obj, in intel_pmdemand_init()
126 &pmdemand_state->base, in intel_pmdemand_init()
138 mutex_init(&display->pmdemand.lock); in intel_pmdemand_init_early()
139 init_waitqueue_head(&display->pmdemand.waitqueue); in intel_pmdemand_init_early()
162 pmdemand_state->active_combo_phys_mask |= BIT(phy); in intel_pmdemand_update_phys_mask()
164 pmdemand_state->active_combo_phys_mask &= ~BIT(phy); in intel_pmdemand_update_phys_mask()
175 pmdemand_state->ddi_clocks[pipe] = port_clock; in intel_pmdemand_update_port_clock()
190 crtc->pipe, in intel_pmdemand_update_max_ddiclk()
191 new_crtc_state->port_clock); in intel_pmdemand_update_max_ddiclk()
193 for (i = 0; i < ARRAY_SIZE(pmdemand_state->ddi_clocks); i++) in intel_pmdemand_update_max_ddiclk()
194 max_ddiclk = max(pmdemand_state->ddi_clocks[i], max_ddiclk); in intel_pmdemand_update_max_ddiclk()
196 pmdemand_state->params.ddiclk_max = DIV_ROUND_UP(max_ddiclk, 1000); in intel_pmdemand_update_max_ddiclk()
206 struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); in intel_pmdemand_update_connector_phys()
207 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in intel_pmdemand_update_connector_phys()
218 if (!crtc_state->hw.active) in intel_pmdemand_update_connector_phys()
235 for_each_oldnew_connector_in_state(&state->base, connector, in intel_pmdemand_update_active_non_tc_phys()
251 pmdemand_state->params.active_phys = in intel_pmdemand_update_active_non_tc_phys()
252 min_t(u16, hweight16(pmdemand_state->active_combo_phys_mask), in intel_pmdemand_update_active_non_tc_phys()
272 for_each_oldnew_connector_in_state(&state->base, connector, in intel_pmdemand_connector_needs_update()
275 to_intel_encoder(old_conn_state->best_encoder); in intel_pmdemand_connector_needs_update()
277 to_intel_encoder(new_conn_state->best_encoder); in intel_pmdemand_connector_needs_update()
305 if (new_bw_state && new_bw_state->qgv_point_peakbw != in intel_pmdemand_needs_update()
306 old_bw_state->qgv_point_peakbw) in intel_pmdemand_needs_update()
312 new_dbuf_state->active_pipes != old_dbuf_state->active_pipes) in intel_pmdemand_needs_update()
317 new_dbuf_state->enabled_slices != in intel_pmdemand_needs_update()
318 old_dbuf_state->enabled_slices) in intel_pmdemand_needs_update()
325 (new_cdclk_state->actual.cdclk != in intel_pmdemand_needs_update()
326 old_cdclk_state->actual.cdclk || in intel_pmdemand_needs_update()
327 new_cdclk_state->actual.voltage_level != in intel_pmdemand_needs_update()
328 old_cdclk_state->actual.voltage_level)) in intel_pmdemand_needs_update()
333 if (new_crtc_state->port_clock != old_crtc_state->port_clock) in intel_pmdemand_needs_update()
362 new_pmdemand_state->params.qclk_gv_index = 0; in intel_pmdemand_atomic_check()
363 new_pmdemand_state->params.qclk_gv_bw = new_bw_state->qgv_point_peakbw; in intel_pmdemand_atomic_check()
370 new_pmdemand_state->params.active_dbufs = in intel_pmdemand_atomic_check()
371 min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3); in intel_pmdemand_atomic_check()
372 new_pmdemand_state->params.active_pipes = in intel_pmdemand_atomic_check()
373 min_t(u8, hweight8(new_dbuf_state->active_pipes), 3); in intel_pmdemand_atomic_check()
375 new_pmdemand_state->params.active_pipes = in intel_pmdemand_atomic_check()
376 min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(display)); in intel_pmdemand_atomic_check()
383 new_pmdemand_state->params.voltage_index = in intel_pmdemand_atomic_check()
384 new_cdclk_state->actual.voltage_level; in intel_pmdemand_atomic_check()
385 new_pmdemand_state->params.cdclk_freq_mhz = in intel_pmdemand_atomic_check()
386 DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000); in intel_pmdemand_atomic_check()
396 new_pmdemand_state->params.plls = in intel_pmdemand_atomic_check()
397 min_t(u16, new_pmdemand_state->params.active_phys + 1, 7); in intel_pmdemand_atomic_check()
403 new_pmdemand_state->params.scalers = 7; in intel_pmdemand_atomic_check()
405 if (state->base.allow_modeset) in intel_pmdemand_atomic_check()
406 return intel_atomic_serialize_global_state(&new_pmdemand_state->base); in intel_pmdemand_atomic_check()
408 return intel_atomic_lock_global_state(&new_pmdemand_state->base); in intel_pmdemand_atomic_check()
430 mutex_lock(&display->pmdemand.lock); in intel_pmdemand_init_pmdemand_params()
431 if (drm_WARN_ON(display->drm, in intel_pmdemand_init_pmdemand_params()
433 memset(&pmdemand_state->params, 0, in intel_pmdemand_init_pmdemand_params()
434 sizeof(pmdemand_state->params)); in intel_pmdemand_init_pmdemand_params()
442 pmdemand_state->params.qclk_gv_bw = in intel_pmdemand_init_pmdemand_params()
444 pmdemand_state->params.voltage_index = in intel_pmdemand_init_pmdemand_params()
446 pmdemand_state->params.qclk_gv_index = in intel_pmdemand_init_pmdemand_params()
448 pmdemand_state->params.active_phys = in intel_pmdemand_init_pmdemand_params()
451 pmdemand_state->params.cdclk_freq_mhz = in intel_pmdemand_init_pmdemand_params()
453 pmdemand_state->params.ddiclk_max = in intel_pmdemand_init_pmdemand_params()
457 pmdemand_state->params.active_pipes = in intel_pmdemand_init_pmdemand_params()
460 pmdemand_state->params.active_pipes = in intel_pmdemand_init_pmdemand_params()
462 pmdemand_state->params.active_dbufs = in intel_pmdemand_init_pmdemand_params()
465 pmdemand_state->params.scalers = in intel_pmdemand_init_pmdemand_params()
470 mutex_unlock(&display->pmdemand.lock); in intel_pmdemand_init_pmdemand_params()
481 if (!wait_event_timeout(display->pmdemand.waitqueue, in intel_pmdemand_wait()
484 drm_err(display->drm, in intel_pmdemand_wait()
494 /* PM Demand only tracks active dbufs on pre-Xe3 platforms */ in intel_pmdemand_program_dbuf()
498 mutex_lock(&display->pmdemand.lock); in intel_pmdemand_program_dbuf()
499 if (drm_WARN_ON(display->drm, in intel_pmdemand_program_dbuf()
512 mutex_unlock(&display->pmdemand.lock); in intel_pmdemand_program_dbuf()
519 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
523 * post plane updates. During the pre plane, as DE might still be in intel_pmdemand_update_params()
533 * as well. So in pre-plane case, we need to check the max of old, new in intel_pmdemand_update_params()
534 * and current register value if not serialized. In post plane update in intel_pmdemand_update_params()
536 * serialized in intel_pmdemand_update_params()
540 u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \ in intel_pmdemand_update_params()
541 u32 old_val = old ? old->params.field : 0; \ in intel_pmdemand_update_params()
542 u32 new_val = new->params.field; \ in intel_pmdemand_update_params()
575 bool serialized) in intel_pmdemand_program_params() argument
581 mutex_lock(&display->pmdemand.lock); in intel_pmdemand_program_params()
582 if (drm_WARN_ON(display->drm, in intel_pmdemand_program_params()
593 serialized); in intel_pmdemand_program_params()
611 drm_dbg_kms(display->drm, in intel_pmdemand_program_params()
621 mutex_unlock(&display->pmdemand.lock); in intel_pmdemand_program_params()
628 return memcmp(&new->params, &old->params, sizeof(new->params)) != 0; in intel_pmdemand_state_changed()
647 WARN_ON(!new_pmdemand_state->base.changed); in intel_pmdemand_pre_plane_update()
670 WARN_ON(!new_pmdemand_state->base.changed); in intel_pmdemand_post_plane_update()