Lines Matching defs:source

58 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
61 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
62 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
64 	switch (*source) {
80 				      enum intel_pipe_crc_source *source)
86 	*source = INTEL_PIPE_CRC_SOURCE_PIPE;
100 			*source = INTEL_PIPE_CRC_SOURCE_TV;
107 				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
110 				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
113 				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
130 				enum intel_pipe_crc_source *source,
135 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
136 		i9xx_pipe_crc_auto_source(display, pipe, source);
138 	switch (*source) {
197 				 enum intel_pipe_crc_source *source,
200 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
201 		i9xx_pipe_crc_auto_source(display, pipe, source);
203 	switch (*source) {
217 		 * The DP CRC source doesn't work on g4x.
219 		 * the correct CRC source before the port is enabled,
220 		 * and not touching the CRC source bits again until
255 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
258 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
259 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
261 	switch (*source) {
338 				enum intel_pipe_crc_source *source,
341 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
342 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
344 	switch (*source) {
366 				enum intel_pipe_crc_source *source,
369 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
370 		*source = INTEL_PIPE_CRC_SOURCE_PIPE;
372 	switch (*source) {
409 			       enum intel_pipe_crc_source *source, u32 *val)
412 		return i8xx_pipe_crc_ctl_reg(source, val);
414 		return i9xx_pipe_crc_ctl_reg(display, pipe, source, val);
416 		return vlv_pipe_crc_ctl_reg(display, pipe, source, val);
418 		return ilk_pipe_crc_ctl_reg(source, val);
420 		return ivb_pipe_crc_ctl_reg(display, pipe, source, val);
422 		return skl_pipe_crc_ctl_reg(display, pipe, source, val);
451 				 const enum intel_pipe_crc_source source)
453 	switch (source) {
463 				 const enum intel_pipe_crc_source source)
465 	switch (source) {
476 				const enum intel_pipe_crc_source source)
478 	switch (source) {
491 				const enum intel_pipe_crc_source source)
493 	switch (source) {
505 				const enum intel_pipe_crc_source source)
507 	switch (source) {
519 				const enum intel_pipe_crc_source source)
521 	switch (source) {
539 			  const enum intel_pipe_crc_source source)
542 		return i8xx_crc_source_valid(display, source);
544 		return i9xx_crc_source_valid(display, source);
546 		return vlv_crc_source_valid(display, source);
548 		return ilk_crc_source_valid(display, source);
550 		return ivb_crc_source_valid(display, source);
552 		return skl_crc_source_valid(display, source);
566 	enum intel_pipe_crc_source source;
568 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
569 		drm_dbg_kms(display->drm, "unknown source %s\n", source_name);
573 	if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
574 	    intel_is_valid_crc_source(display, source) == 0) {
588 	enum intel_pipe_crc_source source;
595 	if (display_crc_ctl_parse_source(source_name, &source) < 0) {
596 		drm_dbg_kms(display->drm, "unknown source %s\n", source_name);
608 	enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
612 	ret = get_new_crc_ctl_reg(display, pipe, &source, &val);
616 	pipe_crc->source = source;
620 	if (!source) {
646 	if (get_new_crc_ctl_reg(display, pipe, &pipe_crc->source, &val) < 0)