26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
104 /* DCLRKM (dst-key) register */
174 	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
176 	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
178 	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
180 	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
182 	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
186 	struct intel_display *display;  member
194 	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
208 static void i830_overlay_clock_gating(struct intel_display *display,  in i830_overlay_clock_gating()  argument
211 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);  in i830_overlay_clock_gating()
216 		intel_de_write(display, DSPCLK_GATE_D(display), 0);  in i830_overlay_clock_gating()
218 		intel_de_write(display, DSPCLK_GATE_D(display),  in i830_overlay_clock_gating()
222 	pci_bus_read_config_byte(pdev->bus,  in i830_overlay_clock_gating()
228 	pci_bus_write_config_byte(pdev->bus,  in i830_overlay_clock_gating()
238 	overlay->flip_complete = fn;  in alloc_request()
240 	rq = i915_request_create(overlay->context);  in alloc_request()
244 	err = i915_active_add_request(&overlay->last_flip, rq);  in alloc_request()
256 	struct intel_display *display = overlay->display;  in intel_overlay_on()  local
260 	drm_WARN_ON(display->drm, overlay->active);  in intel_overlay_on()
272 	overlay->active = true;  in intel_overlay_on()
274 	if (display->platform.i830)  in intel_overlay_on()
275 		i830_overlay_clock_gating(display, false);  in intel_overlay_on()
278 	*cs++ = overlay->flip_addr | OFC_UPDATE;  in intel_overlay_on()
285 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_on()
291 	struct intel_display *display = overlay->display;  in intel_overlay_flip_prepare()  local
292 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_overlay_flip_prepare()
293 	enum pipe pipe = overlay->crtc->pipe;  in intel_overlay_flip_prepare()
296 	drm_WARN_ON(display->drm, overlay->old_vma);  in intel_overlay_flip_prepare()
299 		frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj));  in intel_overlay_flip_prepare()
301 	intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,  in intel_overlay_flip_prepare()
304 	if (overlay->frontbuffer)  in intel_overlay_flip_prepare()
305 		intel_frontbuffer_put(overlay->frontbuffer);  in intel_overlay_flip_prepare()
306 	overlay->frontbuffer = frontbuffer;  in intel_overlay_flip_prepare()
310 	overlay->old_vma = overlay->vma;  in intel_overlay_flip_prepare()
312 		overlay->vma = i915_vma_get(vma);  in intel_overlay_flip_prepare()
314 		overlay->vma = NULL;  in intel_overlay_flip_prepare()
322 	struct intel_display *display = overlay->display;  in intel_overlay_continue()  local
324 	u32 flip_addr = overlay->flip_addr;  in intel_overlay_continue()
327 	drm_WARN_ON(display->drm, !overlay->active);  in intel_overlay_continue()
333 	tmp = intel_de_read(display, DOVSTA);  in intel_overlay_continue()
335 		drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp);  in intel_overlay_continue()
359 	struct intel_display *display = overlay->display;  in intel_overlay_release_old_vma()  local
360 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_overlay_release_old_vma()
363 	vma = fetch_and_zero(&overlay->old_vma);  in intel_overlay_release_old_vma()
364 	if (drm_WARN_ON(display->drm, !vma))  in intel_overlay_release_old_vma()
367 	intel_frontbuffer_flip_complete(i915, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));  in intel_overlay_release_old_vma()
381 	struct intel_display *display = overlay->display;  in intel_overlay_off_tail()  local
385 	overlay->crtc->overlay = NULL;  in intel_overlay_off_tail()
386 	overlay->crtc = NULL;  in intel_overlay_off_tail()
387 	overlay->active = false;  in intel_overlay_off_tail()
389 	if (display->platform.i830)  in intel_overlay_off_tail()
390 		i830_overlay_clock_gating(display, true);  in intel_overlay_off_tail()
398 	if (overlay->flip_complete)  in intel_overlay_last_flip_retire()
399 		overlay->flip_complete(overlay);  in intel_overlay_last_flip_retire()
405 	struct intel_display *display = overlay->display;  in intel_overlay_off()  local
407 	u32 *cs, flip_addr = overlay->flip_addr;  in intel_overlay_off()
409 	drm_WARN_ON(display->drm, !overlay->active);  in intel_overlay_off()
442 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_off()
449 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_recover_from_interrupt()
458 	struct intel_display *display = overlay->display;  in intel_overlay_release_old_vid()  local
466 	if (!overlay->old_vma)  in intel_overlay_release_old_vid()
469 	if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {  in intel_overlay_release_old_vid()
490 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_release_old_vid()
493 void intel_overlay_reset(struct intel_display *display)  in intel_overlay_reset()  argument
495 	struct intel_overlay *overlay = display->overlay;  in intel_overlay_reset()
500 	overlay->old_xscale = 0;  in intel_overlay_reset()
501 	overlay->old_yscale = 0;  in intel_overlay_reset()
502 	overlay->crtc = NULL;  in intel_overlay_reset()
503 	overlay->active = false;  in intel_overlay_reset()
514 		return -EINVAL;  in packed_depth_bytes()
524 		return -EINVAL;  in packed_width_bytes()
538 		return -EINVAL;  in uv_hsubsampling()
552 		return -EINVAL;  in uv_vsubsampling()
556 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width)  in calc_swidthsw()  argument
560 	if (DISPLAY_VER(display) == 2)  in calc_swidthsw()
568 	return (sw - 32) >> 3;  in calc_swidthsw()
613 	memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));  in update_polyphase_filter()
614 	memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,  in update_polyphase_filter()
627 	int uv_hscale = uv_hsubsampling(params->flags);  in update_scaling_factors()
628 	int uv_vscale = uv_vsubsampling(params->flags);  in update_scaling_factors()
630 	if (params->dst_width > 1)  in update_scaling_factors()
631 		xscale = ((params->src_scan_width - 1) << FP_SHIFT) /  in update_scaling_factors()
632 			params->dst_width;  in update_scaling_factors()
636 	if (params->dst_height > 1)  in update_scaling_factors()
637 		yscale = ((params->src_scan_height - 1) << FP_SHIFT) /  in update_scaling_factors()
638 			params->dst_height;  in update_scaling_factors()
642 	/*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/  in update_scaling_factors()
653 	if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)  in update_scaling_factors()
655 	overlay->old_xscale = xscale;  in update_scaling_factors()
656 	overlay->old_yscale = yscale;  in update_scaling_factors()
661 		 &regs->YRGBSCALE);  in update_scaling_factors()
666 		 &regs->UVSCALE);  in update_scaling_factors()
670 		 &regs->UVSCALEV);  in update_scaling_factors()
682 		to_intel_plane_state(overlay->crtc->base.primary->state);  in update_colorkey()
683 	u32 key = overlay->color_key;  in update_colorkey()
687 	if (overlay->color_key_enabled)  in update_colorkey()
690 	if (state->uapi.visible)  in update_colorkey()
691 		format = state->hw.fb->format->format;  in update_colorkey()
716 	iowrite32(key, &regs->DCLRKV);  in update_colorkey()
717 	iowrite32(flags, &regs->DCLRKM);  in update_colorkey()
724 	if (params->flags & I915_OVERLAY_YUV_PLANAR) {  in overlay_cmd_reg()
725 		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {  in overlay_cmd_reg()
738 		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {  in overlay_cmd_reg()
747 		switch (params->flags & I915_OVERLAY_SWAP_MASK) {  in overlay_cmd_reg()
779 	if (ret == -EDEADLK) {  in intel_overlay_pin_fb()
795 	struct intel_display *display = overlay->display;  in intel_overlay_do_put_image()  local
796 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_overlay_do_put_image()
797 	struct overlay_registers __iomem *regs = overlay->regs;  in intel_overlay_do_put_image()
799 	enum pipe pipe = overlay->crtc->pipe;  in intel_overlay_do_put_image()
804 	drm_WARN_ON(display->drm,  in intel_overlay_do_put_image()
805 		    !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));  in intel_overlay_do_put_image()
811 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);  in intel_overlay_do_put_image()
821 	if (!overlay->active) {  in intel_overlay_do_put_image()
823 			overlay->crtc->config;  in intel_overlay_do_put_image()
826 		if (crtc_state->gamma_enable &&  in intel_overlay_do_put_image()
827 		    crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)  in intel_overlay_do_put_image()
829 		if (crtc_state->gamma_enable)  in intel_overlay_do_put_image()
831 		if (DISPLAY_VER(display) == 4)  in intel_overlay_do_put_image()
835 		iowrite32(oconfig, &regs->OCONFIG);  in intel_overlay_do_put_image()
842 	iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);  in intel_overlay_do_put_image()
843 	iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);  in intel_overlay_do_put_image()
845 	if (params->flags & I915_OVERLAY_YUV_PACKED)  in intel_overlay_do_put_image()
846 		tmp_width = packed_width_bytes(params->flags,  in intel_overlay_do_put_image()
847 					       params->src_width);  in intel_overlay_do_put_image()
849 		tmp_width = params->src_width;  in intel_overlay_do_put_image()
851 	swidth = params->src_width;  in intel_overlay_do_put_image()
852 	swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width);  in intel_overlay_do_put_image()
853 	sheight = params->src_height;  in intel_overlay_do_put_image()
854 	iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);  in intel_overlay_do_put_image()
855 	ostride = params->stride_Y;  in intel_overlay_do_put_image()
857 	if (params->flags & I915_OVERLAY_YUV_PLANAR) {  in intel_overlay_do_put_image()
858 		int uv_hscale = uv_hsubsampling(params->flags);  in intel_overlay_do_put_image()
859 		int uv_vscale = uv_vsubsampling(params->flags);  in intel_overlay_do_put_image()
862 		swidth |= (params->src_width / uv_hscale) << 16;  in intel_overlay_do_put_image()
863 		sheight |= (params->src_height / uv_vscale) << 16;  in intel_overlay_do_put_image()
865 		tmp_U = calc_swidthsw(display, params->offset_U,  in intel_overlay_do_put_image()
866 				      params->src_width / uv_hscale);  in intel_overlay_do_put_image()
867 		tmp_V = calc_swidthsw(display, params->offset_V,  in intel_overlay_do_put_image()
868 				      params->src_width / uv_hscale);  in intel_overlay_do_put_image()
871 		iowrite32(i915_ggtt_offset(vma) + params->offset_U,  in intel_overlay_do_put_image()
872 			  &regs->OBUF_0U);  in intel_overlay_do_put_image()
873 		iowrite32(i915_ggtt_offset(vma) + params->offset_V,  in intel_overlay_do_put_image()
874 			  &regs->OBUF_0V);  in intel_overlay_do_put_image()
876 		ostride |= params->stride_UV << 16;  in intel_overlay_do_put_image()
879 	iowrite32(swidth, &regs->SWIDTH);  in intel_overlay_do_put_image()
880 	iowrite32(swidthsw, &regs->SWIDTHSW);  in intel_overlay_do_put_image()
881 	iowrite32(sheight, &regs->SHEIGHT);  in intel_overlay_do_put_image()
882 	iowrite32(ostride, &regs->OSTRIDE);  in intel_overlay_do_put_image()
888 	iowrite32(overlay_cmd_reg(params), &regs->OCMD);  in intel_overlay_do_put_image()
899 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);  in intel_overlay_do_put_image()
906 	struct intel_display *display = overlay->display;  in intel_overlay_switch_off()  local
909 	drm_WARN_ON(display->drm,  in intel_overlay_switch_off()
910 		    !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));  in intel_overlay_switch_off()
916 	if (!overlay->active)  in intel_overlay_switch_off()
923 	iowrite32(0, &overlay->regs->OCMD);  in intel_overlay_switch_off()
931 	if (!crtc->active)  in check_overlay_possible_on_crtc()
932 		return -EINVAL;  in check_overlay_possible_on_crtc()
935 	if (crtc->config->double_wide)  in check_overlay_possible_on_crtc()
936 		return -EINVAL;  in check_overlay_possible_on_crtc()
943 	struct intel_display *display = overlay->display;  in update_pfit_vscale_ratio()  local
949 	if (DISPLAY_VER(display) >= 4) {  in update_pfit_vscale_ratio()
950 		u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));  in update_pfit_vscale_ratio()
957 		if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)  in update_pfit_vscale_ratio()
958 			tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));  in update_pfit_vscale_ratio()
960 			tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));  in update_pfit_vscale_ratio()
965 	overlay->pfit_vscale_ratio = ratio;  in update_pfit_vscale_ratio()
972 		overlay->crtc->config;  in check_overlay_dst()
975 	drm_rect_init(&req, rec->dst_x, rec->dst_y,  in check_overlay_dst()
976 		      rec->dst_width, rec->dst_height);  in check_overlay_dst()
980 	if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src))  in check_overlay_dst()
981 		return -EINVAL;  in check_overlay_dst()
984 		return -EINVAL;  in check_overlay_dst()
994 	tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;  in check_overlay_scaling()
996 		return -EINVAL;  in check_overlay_scaling()
998 	tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;  in check_overlay_scaling()
1000 		return -EINVAL;  in check_overlay_scaling()
1005 static int check_overlay_src(struct intel_display *display,  in check_overlay_src()  argument
1009 	int uv_hscale = uv_hsubsampling(rec->flags);  in check_overlay_src()
1010 	int uv_vscale = uv_vsubsampling(rec->flags);  in check_overlay_src()
1012 	int depth;  in check_overlay_src()  local
1016 	if (display->platform.i845g || display->platform.i830) {  in check_overlay_src()
1017 		if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||  in check_overlay_src()
1018 		    rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)  in check_overlay_src()
1019 			return -EINVAL;  in check_overlay_src()
1021 		if (rec->src_height > IMAGE_MAX_HEIGHT ||  in check_overlay_src()
1022 		    rec->src_width  > IMAGE_MAX_WIDTH)  in check_overlay_src()
1023 			return -EINVAL;  in check_overlay_src()
1027 	if (rec->src_height < N_VERT_Y_TAPS*4 ||  in check_overlay_src()
1028 	    rec->src_width  < N_HORIZ_Y_TAPS*4)  in check_overlay_src()
1029 		return -EINVAL;  in check_overlay_src()
1032 	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {  in check_overlay_src()
1035 		return -EINVAL;  in check_overlay_src()
1039 			return -EINVAL;  in check_overlay_src()
1041 		depth = packed_depth_bytes(rec->flags);  in check_overlay_src()
1042 		if (depth < 0)  in check_overlay_src()
1043 			return depth;  in check_overlay_src()
1046 		rec->stride_UV = 0;  in check_overlay_src()
1047 		rec->offset_U = 0;  in check_overlay_src()
1048 		rec->offset_V = 0;  in check_overlay_src()
1050 		if (rec->offset_Y % depth)  in check_overlay_src()
1051 			return -EINVAL;  in check_overlay_src()
1056 			return -EINVAL;  in check_overlay_src()
1061 		return -EINVAL;  in check_overlay_src()
1064 	if (rec->src_width % uv_hscale)  in check_overlay_src()
1065 		return -EINVAL;  in check_overlay_src()
1068 	if (display->platform.i830 || display->platform.i845g)  in check_overlay_src()
1073 	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)  in check_overlay_src()
1074 		return -EINVAL;  in check_overlay_src()
1075 	if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512)  in check_overlay_src()
1076 		return -EINVAL;  in check_overlay_src()
1078 	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?  in check_overlay_src()
1080 	if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)  in check_overlay_src()
1081 		return -EINVAL;  in check_overlay_src()
1084 	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {  in check_overlay_src()
1087 		/* always 4 Y values per depth pixels */  in check_overlay_src()
1088 		if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)  in check_overlay_src()
1089 			return -EINVAL;  in check_overlay_src()
1091 		tmp = rec->stride_Y*rec->src_height;  in check_overlay_src()
1092 		if (rec->offset_Y + tmp > new_bo->base.size)  in check_overlay_src()
1093 			return -EINVAL;  in check_overlay_src()
1097 		if (rec->src_width > rec->stride_Y)  in check_overlay_src()
1098 			return -EINVAL;  in check_overlay_src()
1099 		if (rec->src_width/uv_hscale > rec->stride_UV)  in check_overlay_src()
1100 			return -EINVAL;  in check_overlay_src()
1102 		tmp = rec->stride_Y * rec->src_height;  in check_overlay_src()
1103 		if (rec->offset_Y + tmp > new_bo->base.size)  in check_overlay_src()
1104 			return -EINVAL;  in check_overlay_src()
1106 		tmp = rec->stride_UV * (rec->src_height / uv_vscale);  in check_overlay_src()
1107 		if (rec->offset_U + tmp > new_bo->base.size ||  in check_overlay_src()
1108 		    rec->offset_V + tmp > new_bo->base.size)  in check_overlay_src()
1109 			return -EINVAL;  in check_overlay_src()
1119 	struct intel_display *display = to_intel_display(dev);  in intel_overlay_put_image_ioctl()  local
1127 	overlay = display->overlay;  in intel_overlay_put_image_ioctl()
1129 		drm_dbg(display->drm, "userspace bug: no overlay\n");  in intel_overlay_put_image_ioctl()
1130 		return -ENODEV;  in intel_overlay_put_image_ioctl()
1133 	if (!(params->flags & I915_OVERLAY_ENABLE)) {  in intel_overlay_put_image_ioctl()
1141 	drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);  in intel_overlay_put_image_ioctl()
1143 		return -ENOENT;  in intel_overlay_put_image_ioctl()
1146 	new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);  in intel_overlay_put_image_ioctl()
1148 		return -ENOENT;  in intel_overlay_put_image_ioctl()
1153 		drm_dbg_kms(display->drm,  in intel_overlay_put_image_ioctl()
1155 		ret = -EINVAL;  in intel_overlay_put_image_ioctl()
1163 	if (overlay->crtc != crtc) {  in intel_overlay_put_image_ioctl()
1172 		overlay->crtc = crtc;  in intel_overlay_put_image_ioctl()
1173 		crtc->overlay = overlay;  in intel_overlay_put_image_ioctl()
1175 		/* line too wide, i.e. one-line-mode */  in intel_overlay_put_image_ioctl()
1176 		if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&  in intel_overlay_put_image_ioctl()
1177 		    crtc->config->gmch_pfit.control & PFIT_ENABLE) {  in intel_overlay_put_image_ioctl()
1178 			overlay->pfit_active = true;  in intel_overlay_put_image_ioctl()
1181 			overlay->pfit_active = false;  in intel_overlay_put_image_ioctl()
1188 	if (overlay->pfit_active) {  in intel_overlay_put_image_ioctl()
1189 		params->dst_y = (((u32)params->dst_y << 12) /  in intel_overlay_put_image_ioctl()
1190 				 overlay->pfit_vscale_ratio);  in intel_overlay_put_image_ioctl()
1192 		params->dst_height = (((u32)params->dst_height << 12) /  in intel_overlay_put_image_ioctl()
1193 				 overlay->pfit_vscale_ratio) + 1;  in intel_overlay_put_image_ioctl()
1196 	if (params->src_scan_height > params->src_height ||  in intel_overlay_put_image_ioctl()
1197 	    params->src_scan_width > params->src_width) {  in intel_overlay_put_image_ioctl()
1198 		ret = -EINVAL;  in intel_overlay_put_image_ioctl()
1202 	ret = check_overlay_src(display, params, new_bo);  in intel_overlay_put_image_ioctl()
1206 	/* Check scaling after src size to prevent a divide-by-zero. */  in intel_overlay_put_image_ioctl()
1230 	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),  in update_reg_attrs()
1231 		  &regs->OCLRC0);  in update_reg_attrs()
1232 	iowrite32(overlay->saturation, &regs->OCLRC1);  in update_reg_attrs()
1264 	if (!check_gamma_bounds(0, attrs->gamma0) ||  in check_gamma()
1265 	    !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||  in check_gamma()
1266 	    !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||  in check_gamma()
1267 	    !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||  in check_gamma()
1268 	    !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||  in check_gamma()
1269 	    !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||  in check_gamma()
1270 	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))  in check_gamma()
1271 		return -EINVAL;  in check_gamma()
1273 	if (!check_gamma5_errata(attrs->gamma5))  in check_gamma()
1274 		return -EINVAL;  in check_gamma()
1282 	struct intel_display *display = to_intel_display(dev);  in intel_overlay_attrs_ioctl()  local
1287 	overlay = display->overlay;  in intel_overlay_attrs_ioctl()
1289 		drm_dbg(display->drm, "userspace bug: no overlay\n");  in intel_overlay_attrs_ioctl()
1290 		return -ENODEV;  in intel_overlay_attrs_ioctl()
1295 	ret = -EINVAL;  in intel_overlay_attrs_ioctl()
1296 	if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {  in intel_overlay_attrs_ioctl()
1297 		attrs->color_key  = overlay->color_key;  in intel_overlay_attrs_ioctl()
1298 		attrs->brightness = overlay->brightness;  in intel_overlay_attrs_ioctl()
1299 		attrs->contrast   = overlay->contrast;  in intel_overlay_attrs_ioctl()
1300 		attrs->saturation = overlay->saturation;  in intel_overlay_attrs_ioctl()
1302 		if (DISPLAY_VER(display) != 2) {  in intel_overlay_attrs_ioctl()
1303 			attrs->gamma0 = intel_de_read(display, OGAMC0);  in intel_overlay_attrs_ioctl()
1304 			attrs->gamma1 = intel_de_read(display, OGAMC1);  in intel_overlay_attrs_ioctl()
1305 			attrs->gamma2 = intel_de_read(display, OGAMC2);  in intel_overlay_attrs_ioctl()
1306 			attrs->gamma3 = intel_de_read(display, OGAMC3);  in intel_overlay_attrs_ioctl()
1307 			attrs->gamma4 = intel_de_read(display, OGAMC4);  in intel_overlay_attrs_ioctl()
1308 			attrs->gamma5 = intel_de_read(display, OGAMC5);  in intel_overlay_attrs_ioctl()
1311 		if (attrs->brightness < -128 || attrs->brightness > 127)  in intel_overlay_attrs_ioctl()
1313 		if (attrs->contrast > 255)  in intel_overlay_attrs_ioctl()
1315 		if (attrs->saturation > 1023)  in intel_overlay_attrs_ioctl()
1318 		overlay->color_key  = attrs->color_key;  in intel_overlay_attrs_ioctl()
1319 		overlay->brightness = attrs->brightness;  in intel_overlay_attrs_ioctl()
1320 		overlay->contrast   = attrs->contrast;  in intel_overlay_attrs_ioctl()
1321 		overlay->saturation = attrs->saturation;  in intel_overlay_attrs_ioctl()
1323 		update_reg_attrs(overlay, overlay->regs);  in intel_overlay_attrs_ioctl()
1325 		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {  in intel_overlay_attrs_ioctl()
1326 			if (DISPLAY_VER(display) == 2)  in intel_overlay_attrs_ioctl()
1329 			if (overlay->active) {  in intel_overlay_attrs_ioctl()
1330 				ret = -EBUSY;  in intel_overlay_attrs_ioctl()
1338 			intel_de_write(display, OGAMC0, attrs->gamma0);  in intel_overlay_attrs_ioctl()
1339 			intel_de_write(display, OGAMC1, attrs->gamma1);  in intel_overlay_attrs_ioctl()
1340 			intel_de_write(display, OGAMC2, attrs->gamma2);  in intel_overlay_attrs_ioctl()
1341 			intel_de_write(display, OGAMC3, attrs->gamma3);  in intel_overlay_attrs_ioctl()
1342 			intel_de_write(display, OGAMC4, attrs->gamma4);  in intel_overlay_attrs_ioctl()
1343 			intel_de_write(display, OGAMC5, attrs->gamma5);  in intel_overlay_attrs_ioctl()
1346 	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;  in intel_overlay_attrs_ioctl()
1357 	struct intel_display *display = overlay->display;  in get_registers()  local
1358 	struct drm_i915_private *i915 = to_i915(display->drm);  in get_registers()
1359 	struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV);  in get_registers()
1363 	if (!display->platform.meteorlake) /* Wa_22018444074 */  in get_registers()
1377 		overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);  in get_registers()
1379 		overlay->flip_addr = i915_ggtt_offset(vma);  in get_registers()
1380 	overlay->regs = i915_vma_pin_iomap(vma);  in get_registers()
1383 	if (IS_ERR(overlay->regs)) {  in get_registers()
1384 		err = PTR_ERR(overlay->regs);  in get_registers()
1388 	overlay->reg_bo = obj;  in get_registers()
1396 void intel_overlay_setup(struct intel_display *display)  in intel_overlay_setup()  argument
1398 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_overlay_setup()
1403 	if (!HAS_OVERLAY(display))  in intel_overlay_setup()
1406 	engine = to_gt(dev_priv)->engine[RCS0];  in intel_overlay_setup()
1407 	if (!engine || !engine->kernel_context)  in intel_overlay_setup()
1414 	overlay->display = display;  in intel_overlay_setup()
1415 	overlay->context = engine->kernel_context;  in intel_overlay_setup()
1416 	overlay->color_key = 0x0101fe;  in intel_overlay_setup()
1417 	overlay->color_key_enabled = true;  in intel_overlay_setup()
1418 	overlay->brightness = -19;  in intel_overlay_setup()
1419 	overlay->contrast = 75;  in intel_overlay_setup()
1420 	overlay->saturation = 146;  in intel_overlay_setup()
1422 	i915_active_init(&overlay->last_flip,  in intel_overlay_setup()
1425 	ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display));  in intel_overlay_setup()
1429 	memset_io(overlay->regs, 0, sizeof(struct overlay_registers));  in intel_overlay_setup()
1430 	update_polyphase_filter(overlay->regs);  in intel_overlay_setup()
1431 	update_reg_attrs(overlay, overlay->regs);  in intel_overlay_setup()
1433 	display->overlay = overlay;  in intel_overlay_setup()
1434 	drm_info(display->drm, "Initialized overlay support.\n");  in intel_overlay_setup()
1441 bool intel_overlay_available(struct intel_display *display)  in intel_overlay_available()  argument
1443 	return display->overlay;  in intel_overlay_available()
1446 void intel_overlay_cleanup(struct intel_display *display)  in intel_overlay_cleanup()  argument
1450 	overlay = fetch_and_zero(&display->overlay);  in intel_overlay_cleanup()
1459 	drm_WARN_ON(display->drm, overlay->active);  in intel_overlay_cleanup()
1461 	i915_gem_object_put(overlay->reg_bo);  in intel_overlay_cleanup()
1462 	i915_active_fini(&overlay->last_flip);  in intel_overlay_cleanup()
1477 intel_overlay_snapshot_capture(struct intel_display *display)  in intel_overlay_snapshot_capture()  argument
1479 	struct intel_overlay *overlay = display->overlay;  in intel_overlay_snapshot_capture()
1482 	if (!overlay || !overlay->active)  in intel_overlay_snapshot_capture()
1489 	error->dovsta = intel_de_read(display, DOVSTA);  in intel_overlay_snapshot_capture()
1490 	error->isr = intel_de_read(display, GEN2_ISR);  in intel_overlay_snapshot_capture()
1491 	error->base = overlay->flip_addr;  in intel_overlay_snapshot_capture()
1493 	memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));  in intel_overlay_snapshot_capture()
1506 		   error->dovsta, error->isr);  in intel_overlay_snapshot_print()
1507 	drm_printf(p, "  Register file at 0x%08lx:\n", error->base);  in intel_overlay_snapshot_print()
1509 #define P(x) drm_printf(p, "    " #x ": 0x%08x\n", error->regs.x)  in intel_overlay_snapshot_print()