Lines Matching refs:i915
40 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
51 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
59 state = drm_atomic_state_alloc(&i915->drm);
61 drm_dbg_kms(&i915->drm,
71 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
80 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
83 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
87 drm_dbg_kms(&i915->drm,
121 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
123 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
127 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
146 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
149 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) {
158 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
160 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
172 intel_update_watermarks(i915);
187 static u8 get_transcoder_pipes(struct drm_i915_private *i915,
193 for_each_intel_crtc(&i915->drm, temp_crtc) {
218 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
237 *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder));
238 drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask));
242 *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask);
245 static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask)
250 for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) {
263 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
271 joiner_secondaries_mask = get_joiner_secondary_pipes(i915,
275 drm_WARN_ON(&i915->drm,
280 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask)
283 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask)
286 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask)
289 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
296 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
301 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
323 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
336 if (DISPLAY_INFO(i915)->color.degamma_lut_size) {
351 drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut &&
370 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
372 struct intel_display *display = &i915->display;
375 if (DISPLAY_VER(i915) >= 4)
378 for_each_intel_crtc(&i915->drm, crtc) {
390 drm_dbg_kms(&i915->drm,
427 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
432 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
470 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
478 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
519 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915,
534 for_each_intel_crtc(&i915->drm, crtc) {
547 for_each_intel_crtc(&i915->drm, crtc) {
557 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
569 return IS_SANDYBRIDGE(i915) &&
578 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
584 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
595 drm_dbg_kms(&i915->drm,
603 drm_dbg_kms(&i915->drm,
620 drm_dbg_kms(&i915->drm,
654 if (HAS_DDI(i915))
659 static void readout_plane_state(struct drm_i915_private *i915)
661 struct intel_display *display = &i915->display;
665 for_each_intel_plane(&i915->drm, plane) {
679 drm_dbg_kms(&i915->drm,
685 for_each_intel_crtc(&i915->drm, crtc) {
693 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
695 struct intel_display *display = &i915->display;
697 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
704 for_each_intel_crtc(&i915->drm, crtc) {
719 drm_dbg_kms(&i915->drm,
725 readout_plane_state(i915);
727 for_each_intel_encoder(&i915->drm, encoder) {
746 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
769 drm_dbg_kms(&i915->drm,
778 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
812 drm_dbg_kms(&i915->drm,
819 for_each_intel_crtc(&i915->drm, crtc) {
842 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
858 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
865 drm_dbg_kms(&i915->drm,
877 intel_wm_get_hw_state(i915);
886 get_encoder_power_domains(struct drm_i915_private *i915)
890 for_each_intel_encoder(&i915->drm, encoder) {
908 static void intel_early_display_was(struct drm_i915_private *i915)
914 if (IS_DISPLAY_VER(i915, 10, 12))
915 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
921 if (IS_HASWELL(i915))
922 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
924 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
926 intel_de_rmw(i915, CHICKEN_PAR1_1,
928 intel_de_rmw(i915, CHICKEN_MISC_2,
934 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
937 struct intel_display *display = &i915->display;
944 intel_early_display_was(i915);
945 intel_modeset_readout_hw_state(i915);
948 get_encoder_power_domains(i915);
950 intel_pch_sanitize(i915);
958 for_each_intel_crtc(&i915->drm, crtc) {
972 intel_fbc_sanitize(&i915->display);
974 intel_sanitize_plane_mapping(i915);
976 for_each_intel_encoder(&i915->drm, encoder)
983 intel_modeset_update_connector_atomic_state(i915);
985 intel_sanitize_all_crtcs(i915, ctx);
991 intel_wm_get_hw_state(i915);
992 intel_wm_sanitize(i915);
994 for_each_intel_crtc(&i915->drm, crtc) {
1000 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))