Lines Matching +full:pps +full:- +full:channel
2 * Copyright © 2006-2007 Intel Corporation
107 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
112 wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain);
116 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
118 intel_display_power_put(display, encoder->power_domain, wakeref);
126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
130 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
132 tmp = intel_de_read(dev_priv, lvds_encoder->reg);
142 crtc_state->hw.adjusted_mode.flags |= flags;
145 crtc_state->gmch_pfit.lvds_border_bits =
152 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
155 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
159 struct intel_lvds_pps *pps)
163 pps->powerdown_on_reset = intel_de_read(dev_priv,
167 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
168 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
169 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
172 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
173 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
180 * too short power-cycle delay due to the asynchronous programming of
184 val--;
186 pps->delays.power_cycle = val * 1000;
189 pps->delays.power_up == 0 &&
190 pps->delays.backlight_on == 0 &&
191 pps->delays.power_down == 0 &&
192 pps->delays.backlight_off == 0) {
193 drm_dbg_kms(&dev_priv->drm,
197 pps->delays.power_up = 40 * 10;
198 pps->delays.backlight_on = 200 * 10;
200 pps->delays.power_down = 35 * 10;
201 pps->delays.backlight_off = 200 * 10;
204 drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d "
206 pps->delays.power_up, pps->delays.power_down,
207 pps->delays.power_cycle, pps->delays.backlight_on,
208 pps->delays.backlight_off, pps->divider,
209 pps->port, pps->powerdown_on_reset);
213 struct intel_lvds_pps *pps)
218 drm_WARN_ON(&dev_priv->drm,
220 if (pps->powerdown_on_reset)
225 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
226 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |
227 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));
230 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |
231 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));
234 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
236 DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));
246 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
247 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
248 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
249 enum pipe pipe = crtc->pipe;
254 assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
259 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
261 temp = lvds_encoder->init_lvds_val;
274 temp |= crtc_state->gmch_pfit.lvds_border_bits;
277 * Set the B0-B3 data pairs corresponding to whether we're going to
278 * set the DPLLs for dual-channel mode or not.
280 if (lvds_encoder->is_dual_link)
286 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
292 temp |= lvds_encoder->a3_power;
296 * special lvds dither control bit on pch-split platforms, dithering is
304 if (crtc_state->dither && crtc_state->pipe_bpp == 18)
310 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
312 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
315 intel_de_write(i915, lvds_encoder->reg, temp);
327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
329 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);
332 intel_de_posting_read(dev_priv, lvds_encoder->reg);
335 drm_err(&dev_priv->drm,
347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
351 drm_err(&dev_priv->drm,
354 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
355 intel_de_posting_read(dev_priv, lvds_encoder->reg);
387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
390 drm_err(&dev_priv->drm,
398 struct intel_display *display = to_intel_display(_connector->dev);
402 int max_pixclk = display->cdclk.max_dotclk_freq;
413 if (fixed_mode->clock > max_pixclk)
423 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
425 struct intel_connector *connector = lvds_encoder->attached_connector;
426 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
427 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
432 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {
433 drm_err(&i915->drm, "Can't support LVDS on pipe A\n");
434 return -EINVAL;
438 crtc_state->has_pch_encoder = true;
440 return -EINVAL;
443 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
448 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
449 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
450 drm_dbg_kms(&i915->drm,
452 crtc_state->pipe_bpp, lvds_bpp);
453 crtc_state->pipe_bpp = lvds_bpp;
456 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
457 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
469 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
470 return -EINVAL;
491 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
495 drm_edid_connector_update(&connector->base, fixed_edid);
497 return drm_edid_connector_add_modes(&connector->base);
527 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
551 .ident = "MSI IM-945GSE-A",
578 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
586 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
591 .ident = "AOpen i915GMm-HFS",
594 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
599 .ident = "AOpen i45GMx-I",
602 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
607 .ident = "Aopen i945GTt-VFA",
638 .ident = "Asus AT5NM10T-I",
641 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
646 .ident = "Hewlett-Packard HP t5740",
648 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
654 .ident = "Hewlett-Packard t5745",
656 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
662 .ident = "Hewlett-Packard st5747",
664 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
672 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
673 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
678 .ident = "Gigabyte GA-D525TUD",
686 .ident = "Supermicro X7SPA-H",
689 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
746 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
782 for_each_intel_encoder(&i915->drm, encoder) {
783 if (encoder->type == INTEL_OUTPUT_LVDS)
794 return encoder && to_lvds_encoder(encoder)->is_dual_link;
799 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);
800 struct intel_connector *connector = lvds_encoder->attached_connector;
806 if (i915->display.params.lvds_channel_mode > 0)
807 return i915->display.params.lvds_channel_mode == 2;
809 /* single channel LVDS is limited to 112 MHz */
810 if (fixed_mode->clock > 112999)
822 val = intel_de_read(i915, lvds_encoder->reg);
828 val = connector->panel.vbt.bios_lvds_val;
839 * intel_lvds_init - setup LVDS connectors on this device
847 struct intel_display *display = &i915->display;
858 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,
863 if (!i915->display.vbt.int_lvds_support) {
864 drm_dbg_kms(&i915->drm,
884 drm_dbg_kms(&i915->drm,
888 drm_dbg_kms(&i915->drm,
902 lvds_encoder->attached_connector = connector;
903 encoder = &lvds_encoder->base;
905 drm_connector_init_with_ddc(&i915->drm, &connector->base,
910 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
913 encoder->enable = intel_enable_lvds;
914 encoder->pre_enable = intel_pre_enable_lvds;
915 encoder->compute_config = intel_lvds_compute_config;
917 encoder->disable = pch_disable_lvds;
918 encoder->post_disable = pch_post_disable_lvds;
920 encoder->disable = gmch_disable_lvds;
922 encoder->get_hw_state = intel_lvds_get_hw_state;
923 encoder->get_config = intel_lvds_get_config;
924 encoder->update_pipe = intel_backlight_update;
925 encoder->shutdown = intel_lvds_shutdown;
926 connector->get_hw_state = intel_connector_get_hw_state;
930 encoder->type = INTEL_OUTPUT_LVDS;
931 encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
932 encoder->port = PORT_NONE;
933 encoder->cloneable = 0;
935 encoder->pipe_mask = BIT(PIPE_B);
937 encoder->pipe_mask = ~0;
939 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);
940 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
942 lvds_encoder->reg = lvds_reg;
944 intel_lvds_add_properties(&connector->base);
946 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);
947 lvds_encoder->init_lvds_val = lvds;
961 mutex_lock(&i915->drm.mode_config.mutex);
963 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);
965 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
967 if (drm_edid_connector_update(&connector->base, drm_edid) ||
968 !drm_edid_connector_add_modes(&connector->base)) {
969 drm_edid_connector_update(&connector->base, NULL);
971 drm_edid = ERR_PTR(-EINVAL);
974 drm_edid = ERR_PTR(-ENOENT);
976 intel_bios_init_panel_late(display, &connector->panel, NULL,
994 mutex_unlock(&i915->drm.mode_config.mutex);
1004 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1005 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",
1006 lvds_encoder->is_dual_link ? "dual" : "single");
1008 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1013 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");
1014 drm_connector_cleanup(&connector->base);
1015 drm_encoder_cleanup(&encoder->base);