Lines Matching refs:display
71 struct intel_display *display = to_intel_display(intel_hdmi); in assert_hdmi_port_disabled() local
74 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; in assert_hdmi_port_disabled()
76 drm_WARN(display->drm, in assert_hdmi_port_disabled()
77 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
82 assert_hdmi_transcoder_func_disabled(struct intel_display *display, in assert_hdmi_transcoder_func_disabled() argument
85 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
86 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
161 hsw_dip_data_reg(struct intel_display *display, in hsw_dip_data_reg() argument
168 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
170 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
172 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
174 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
176 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
178 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
180 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
182 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
189 static int hsw_dip_data_size(struct intel_display *display, in hsw_dip_data_size() argument
200 if (DISPLAY_VER(display) >= 11) in hsw_dip_data_size()
214 struct intel_display *display = to_intel_display(encoder); in g4x_write_infoframe() local
216 u32 val = intel_de_read(display, VIDEO_DIP_CTL); in g4x_write_infoframe()
219 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
227 intel_de_write(display, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
230 intel_de_write(display, VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
235 intel_de_write(display, VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
241 intel_de_write(display, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
242 intel_de_posting_read(display, VIDEO_DIP_CTL); in g4x_write_infoframe()
250 struct intel_display *display = to_intel_display(encoder); in g4x_read_infoframe() local
254 intel_de_rmw(display, VIDEO_DIP_CTL, in g4x_read_infoframe()
258 *data++ = intel_de_read(display, VIDEO_DIP_DATA); in g4x_read_infoframe()
264 struct intel_display *display = to_intel_display(encoder); in g4x_infoframes_enabled() local
265 u32 val = intel_de_read(display, VIDEO_DIP_CTL); in g4x_infoframes_enabled()
282 struct intel_display *display = to_intel_display(encoder); in ibx_write_infoframe() local
286 u32 val = intel_de_read(display, reg); in ibx_write_infoframe()
289 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
297 intel_de_write(display, reg, val); in ibx_write_infoframe()
300 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
306 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
312 intel_de_write(display, reg, val); in ibx_write_infoframe()
313 intel_de_posting_read(display, reg); in ibx_write_infoframe()
321 struct intel_display *display = to_intel_display(encoder); in ibx_read_infoframe() local
326 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in ibx_read_infoframe()
330 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
336 struct intel_display *display = to_intel_display(encoder); in ibx_infoframes_enabled() local
339 u32 val = intel_de_read(display, reg); in ibx_infoframes_enabled()
357 struct intel_display *display = to_intel_display(encoder); in cpt_write_infoframe() local
361 u32 val = intel_de_read(display, reg); in cpt_write_infoframe()
364 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in cpt_write_infoframe()
375 intel_de_write(display, reg, val); in cpt_write_infoframe()
378 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in cpt_write_infoframe()
384 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in cpt_write_infoframe()
390 intel_de_write(display, reg, val); in cpt_write_infoframe()
391 intel_de_posting_read(display, reg); in cpt_write_infoframe()
399 struct intel_display *display = to_intel_display(encoder); in cpt_read_infoframe() local
404 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in cpt_read_infoframe()
408 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
414 struct intel_display *display = to_intel_display(encoder); in cpt_infoframes_enabled() local
416 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); in cpt_infoframes_enabled()
431 struct intel_display *display = to_intel_display(encoder); in vlv_write_infoframe() local
435 u32 val = intel_de_read(display, reg); in vlv_write_infoframe()
438 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in vlv_write_infoframe()
446 intel_de_write(display, reg, val); in vlv_write_infoframe()
449 intel_de_write(display, in vlv_write_infoframe()
455 intel_de_write(display, in vlv_write_infoframe()
462 intel_de_write(display, reg, val); in vlv_write_infoframe()
463 intel_de_posting_read(display, reg); in vlv_write_infoframe()
471 struct intel_display *display = to_intel_display(encoder); in vlv_read_infoframe() local
476 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), in vlv_read_infoframe()
480 *data++ = intel_de_read(display, in vlv_read_infoframe()
487 struct intel_display *display = to_intel_display(encoder); in vlv_infoframes_enabled() local
489 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); in vlv_infoframes_enabled()
507 struct intel_display *display = to_intel_display(encoder); in hsw_write_infoframe() local
510 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); in hsw_write_infoframe()
513 u32 val = intel_de_read(display, ctl_reg); in hsw_write_infoframe()
515 data_size = hsw_dip_data_size(display, type); in hsw_write_infoframe()
517 drm_WARN_ON(display->drm, len > data_size); in hsw_write_infoframe()
520 intel_de_write(display, ctl_reg, val); in hsw_write_infoframe()
523 intel_de_write(display, in hsw_write_infoframe()
524 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), in hsw_write_infoframe()
530 intel_de_write(display, in hsw_write_infoframe()
531 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), in hsw_write_infoframe()
535 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && in hsw_write_infoframe()
542 intel_de_write(display, ctl_reg, val); in hsw_write_infoframe()
543 intel_de_posting_read(display, ctl_reg); in hsw_write_infoframe()
550 struct intel_display *display = to_intel_display(encoder); in hsw_read_infoframe() local
556 *data++ = intel_de_read(display, in hsw_read_infoframe()
557 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); in hsw_read_infoframe()
563 struct intel_display *display = to_intel_display(encoder); in hsw_infoframes_enabled() local
564 u32 val = intel_de_read(display, in hsw_infoframes_enabled()
565 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
572 if (DISPLAY_VER(display) >= 10) in hsw_infoframes_enabled()
575 if (HAS_AS_SDP(display)) in hsw_infoframes_enabled()
607 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_infoframes_enabled() local
618 if (HAS_DDI(display)) { in intel_hdmi_infoframes_enabled()
833 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_drm_infoframe() local
837 if (DISPLAY_VER(display) < 10) in intel_hdmi_compute_drm_infoframe()
851 drm_dbg_kms(display->drm, in intel_hdmi_compute_drm_infoframe()
857 if (drm_WARN_ON(display->drm, ret)) in intel_hdmi_compute_drm_infoframe()
868 struct intel_display *display = to_intel_display(encoder); in g4x_set_infoframes() local
872 u32 val = intel_de_read(display, reg); in g4x_set_infoframes()
892 drm_dbg_kms(display->drm, in g4x_set_infoframes()
899 intel_de_write(display, reg, val); in g4x_set_infoframes()
900 intel_de_posting_read(display, reg); in g4x_set_infoframes()
906 drm_dbg_kms(display->drm, in g4x_set_infoframes()
919 intel_de_write(display, reg, val); in g4x_set_infoframes()
920 intel_de_posting_read(display, reg); in g4x_set_infoframes()
980 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_set_gcp_infoframe() local
989 if (HAS_DDI(display)) in intel_hdmi_set_gcp_infoframe()
990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
998 intel_de_write(display, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
1006 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_read_gcp_infoframe() local
1015 if (HAS_DDI(display)) in intel_hdmi_read_gcp_infoframe()
1016 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1024 crtc_state->infoframes.gcp = intel_de_read(display, reg); in intel_hdmi_read_gcp_infoframe()
1054 struct intel_display *display = to_intel_display(encoder); in ibx_set_infoframes() local
1059 u32 val = intel_de_read(display, reg); in ibx_set_infoframes()
1073 intel_de_write(display, reg, val); in ibx_set_infoframes()
1074 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1079 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
1094 intel_de_write(display, reg, val); in ibx_set_infoframes()
1095 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1113 struct intel_display *display = to_intel_display(encoder); in cpt_set_infoframes() local
1117 u32 val = intel_de_read(display, reg); in cpt_set_infoframes()
1130 intel_de_write(display, reg, val); in cpt_set_infoframes()
1131 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1143 intel_de_write(display, reg, val); in cpt_set_infoframes()
1144 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1162 struct intel_display *display = to_intel_display(encoder); in vlv_set_infoframes() local
1166 u32 val = intel_de_read(display, reg); in vlv_set_infoframes()
1180 intel_de_write(display, reg, val); in vlv_set_infoframes()
1181 intel_de_posting_read(display, reg); in vlv_set_infoframes()
1186 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
1201 intel_de_write(display, reg, val); in vlv_set_infoframes()
1202 intel_de_posting_read(display, reg); in vlv_set_infoframes()
1219 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_fastset_infoframes() local
1220 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, in intel_hdmi_fastset_infoframes()
1222 u32 val = intel_de_read(display, reg); in intel_hdmi_fastset_infoframes()
1231 intel_de_write(display, reg, val); in intel_hdmi_fastset_infoframes()
1232 intel_de_posting_read(display, reg); in intel_hdmi_fastset_infoframes()
1244 struct intel_display *display = to_intel_display(encoder); in hsw_set_infoframes() local
1245 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, in hsw_set_infoframes()
1247 u32 val = intel_de_read(display, reg); in hsw_set_infoframes()
1249 assert_hdmi_transcoder_func_disabled(display, in hsw_set_infoframes()
1258 intel_de_write(display, reg, val); in hsw_set_infoframes()
1259 intel_de_posting_read(display, reg); in hsw_set_infoframes()
1266 intel_de_write(display, reg, val); in hsw_set_infoframes()
1267 intel_de_posting_read(display, reg); in hsw_set_infoframes()
1285 struct intel_display *display = to_intel_display(hdmi); in intel_dp_dual_mode_set_tmds_output() local
1291 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", in intel_dp_dual_mode_set_tmds_output()
1294 drm_dp_dual_mode_set_tmds_output(display->drm, in intel_dp_dual_mode_set_tmds_output()
1360 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_write_an_aksv() local
1368 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", in intel_hdmi_hdcp_write_an_aksv()
1375 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); in intel_hdmi_hdcp_write_an_aksv()
1384 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_bksv() local
1390 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bksv()
1399 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_bstatus() local
1405 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_bstatus()
1415 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_repeater_present() local
1421 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_repeater_present()
1433 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_ri_prime() local
1439 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ri_prime()
1448 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_ksv_ready() local
1454 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ksv_ready()
1466 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_ksv_fifo() local
1471 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_ksv_fifo()
1482 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_v_prime_part() local
1491 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_v_prime_part()
1500 struct intel_display *display = to_intel_display(connector); in kbl_repositioning_enc_en_signal() local
1507 scanline = intel_de_read(display, in kbl_repositioning_enc_en_signal()
1508 PIPEDSL(display, crtc->pipe)); in kbl_repositioning_enc_en_signal()
1517 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1525 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1538 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_toggle_signalling() local
1551 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", in intel_hdmi_hdcp_toggle_signalling()
1571 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_check_link_once() local
1591 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", in intel_hdmi_hdcp_check_link_once()
1659 struct intel_display *display = to_intel_display(dig_port); in hdcp2_detect_msg_availability() local
1665 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", in hdcp2_detect_msg_availability()
1686 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp2_wait_for_msg() local
1701 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_wait_for_msg()
1723 struct intel_display *display = to_intel_display(connector); in intel_hdmi_hdcp2_read_msg() local
1740 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_read_msg()
1749 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", in intel_hdmi_hdcp2_read_msg()
1815 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_source_max_tmds_clock() local
1819 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv)) in intel_hdmi_source_max_tmds_clock()
1821 else if (DISPLAY_VER(display) >= 10) in intel_hdmi_source_max_tmds_clock()
1823 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) in intel_hdmi_source_max_tmds_clock()
1825 else if (DISPLAY_VER(display) >= 5) in intel_hdmi_source_max_tmds_clock()
1881 struct intel_display *display = to_intel_display(hdmi); in hdmi_port_clock_valid() local
1882 struct drm_i915_private *dev_priv = to_i915(display->drm); in hdmi_port_clock_valid()
1919 if (DISPLAY_VER(display) >= 14) in hdmi_port_clock_valid()
1942 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) in intel_hdmi_source_bpc_possible() argument
1946 return !HAS_GMCH(display); in intel_hdmi_source_bpc_possible()
1948 return DISPLAY_VER(display) >= 11; in intel_hdmi_source_bpc_possible()
1994 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_clock_valid() local
2007 if (!intel_hdmi_source_bpc_possible(display, bpc)) in intel_hdmi_mode_clock_valid()
2019 drm_WARN_ON(display->drm, status == MODE_OK); in intel_hdmi_mode_clock_valid()
2028 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_valid() local
2030 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_hdmi_mode_valid()
2033 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_hdmi_mode_valid()
2108 struct intel_display *display = to_intel_display(crtc_state); in hdmi_bpc_possible() local
2112 if (!intel_hdmi_source_bpc_possible(display, bpc)) in hdmi_bpc_possible()
2117 bpc == 10 && DISPLAY_VER(display) == 11 && in hdmi_bpc_possible()
2164 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_clock() local
2187 drm_dbg_kms(display->drm, in intel_hdmi_compute_clock()
2264 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_output_format() local
2275 drm_dbg_kms(display->drm, in intel_hdmi_compute_output_format()
2336 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_config() local
2369 drm_dbg_kms(display->drm, in intel_hdmi_compute_config()
2404 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); in intel_hdmi_compute_config()
2409 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); in intel_hdmi_compute_config()
2414 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); in intel_hdmi_compute_config()
2419 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); in intel_hdmi_compute_config()
2452 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_dp_dual_mode_detect() local
2459 type = drm_dp_dual_mode_detect(display->drm, ddc); in intel_hdmi_dp_dual_mode_detect()
2473 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2486 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); in intel_hdmi_dp_dual_mode_detect()
2488 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2494 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) && in intel_hdmi_dp_dual_mode_detect()
2496 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2505 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_set_edid() local
2518 drm_dbg_kms(display->drm, in intel_hdmi_set_edid()
2547 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_detect() local
2554 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_detect()
2557 if (!intel_display_device_enabled(display)) in intel_hdmi_detect()
2560 if (!intel_display_driver_check_access(display)) in intel_hdmi_detect()
2565 if (DISPLAY_VER(display) >= 11 && in intel_hdmi_detect()
2586 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_force() local
2588 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_force()
2591 if (!intel_display_driver_check_access(display)) in intel_hdmi_force()
2645 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_connector_atomic_check() local
2647 if (HAS_DDI(display)) in intel_hdmi_connector_atomic_check()
2662 struct intel_display *display = to_intel_display(intel_hdmi); in intel_hdmi_add_properties() local
2671 if (DISPLAY_VER(display) >= 10) in intel_hdmi_add_properties()
2674 if (!HAS_GMCH(display)) in intel_hdmi_add_properties()
2701 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_handle_sink_scrambling() local
2708 drm_dbg_kms(display->drm, in intel_hdmi_handle_sink_scrambling()
2789 struct intel_display *display = to_intel_display(encoder); in icl_encoder_to_ddc_pin() local
2797 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); in icl_encoder_to_ddc_pin()
2845 struct intel_display *display = to_intel_display(encoder); in gen9bc_tgp_encoder_to_ddc_pin() local
2849 drm_WARN_ON(display->drm, encoder->port == PORT_A); in gen9bc_tgp_encoder_to_ddc_pin()
2909 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_default_ddc_pin() local
2919 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv)) in intel_hdmi_default_ddc_pin()
2941 struct intel_display *display = to_intel_display(encoder); in get_encoder_by_ddc_pin() local
2944 for_each_intel_encoder(display->drm, other) { in get_encoder_by_ddc_pin()
2955 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) in get_encoder_by_ddc_pin()
2964 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_ddc_pin() local
2977 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) { in intel_hdmi_ddc_pin()
2978 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2986 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2993 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
3003 struct intel_display *display = to_intel_display(dig_port); in intel_infoframe_init() local
3017 } else if (HAS_DDI(display)) { in intel_infoframe_init()
3045 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_init_connector() local
3054 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3058 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) in intel_hdmi_init_connector()
3074 intel_gmbus_get_adapter(display, ddc_pin)); in intel_hdmi_init_connector()
3078 if (DISPLAY_VER(display) < 12) in intel_hdmi_init_connector()
3083 if (DISPLAY_VER(display) >= 10) in intel_hdmi_init_connector()
3089 if (HAS_DDI(display)) in intel_hdmi_init_connector()
3099 if (is_hdcp_supported(display, port)) { in intel_hdmi_init_connector()
3103 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3113 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); in intel_hdmi_init_connector()