Lines Matching +full:hdmi +full:- +full:connector
3 * Copyright © 2006-2009 Intel Corporation
30 #include <linux/hdmi.h>
44 #include <media/cec-notifier.h>
76 drm_WARN(display->drm, in assert_hdmi_port_disabled()
77 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
78 "HDMI port enabled, expecting disabled\n"); in assert_hdmi_port_disabled()
85 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
88 "HDMI transcoder function enabled, expecting disabled\n"); in assert_hdmi_transcoder_func_disabled()
219 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in g4x_infoframes_enabled()
284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
285 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_write_infoframe()
289 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
300 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
306 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_read_infoframe()
326 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in ibx_read_infoframe()
330 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
337 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in ibx_infoframes_enabled()
344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in ibx_infoframes_enabled()
359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_write_infoframe()
360 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_write_infoframe()
364 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in cpt_write_infoframe()
378 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in cpt_write_infoframe()
384 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in cpt_write_infoframe()
400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_read_infoframe()
404 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in cpt_read_infoframe()
408 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in cpt_infoframes_enabled()
433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_write_infoframe()
434 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_write_infoframe()
438 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in vlv_write_infoframe()
450 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); in vlv_write_infoframe()
456 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); in vlv_write_infoframe()
472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_read_infoframe()
476 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), in vlv_read_infoframe()
481 VLV_TVIDEO_DIP_DATA(crtc->pipe)); in vlv_read_infoframe()
488 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in vlv_infoframes_enabled()
494 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in vlv_infoframes_enabled()
509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_write_infoframe()
517 drm_WARN_ON(display->drm, len > data_size); in hsw_write_infoframe()
535 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && in hsw_write_infoframe()
536 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) in hsw_write_infoframe()
551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_read_infoframe()
565 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
612 val = dig_port->infoframes_enabled(encoder, crtc_state); in intel_hdmi_infoframes_enabled()
632 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
643 * The hdmi pack() functions don't know about that hardware specific hole so we
656 if ((crtc_state->infoframes.enable & in intel_write_infoframe()
660 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) in intel_write_infoframe()
664 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); in intel_write_infoframe()
665 if (drm_WARN_ON(encoder->base.dev, len < 0)) in intel_write_infoframe()
673 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); in intel_write_infoframe()
685 if ((crtc_state->infoframes.enable & in intel_read_infoframe()
689 dig_port->read_infoframe(encoder, crtc_state, in intel_read_infoframe()
696 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); in intel_read_infoframe()
698 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
703 if (frame->any.type != type) in intel_read_infoframe()
704 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
706 frame->any.type, type); in intel_read_infoframe()
714 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; in intel_hdmi_compute_avi_infoframe()
716 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
717 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_avi_infoframe() local
720 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
723 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
726 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, in intel_hdmi_compute_avi_infoframe()
731 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_hdmi_compute_avi_infoframe()
732 frame->colorspace = HDMI_COLORSPACE_YUV420; in intel_hdmi_compute_avi_infoframe()
733 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_hdmi_compute_avi_infoframe()
734 frame->colorspace = HDMI_COLORSPACE_YUV444; in intel_hdmi_compute_avi_infoframe()
736 frame->colorspace = HDMI_COLORSPACE_RGB; in intel_hdmi_compute_avi_infoframe()
741 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && in intel_hdmi_compute_avi_infoframe()
742 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_hdmi_compute_avi_infoframe()
744 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { in intel_hdmi_compute_avi_infoframe()
745 drm_hdmi_avi_infoframe_quant_range(frame, connector, in intel_hdmi_compute_avi_infoframe()
747 crtc_state->limited_color_range ? in intel_hdmi_compute_avi_infoframe()
751 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; in intel_hdmi_compute_avi_infoframe()
752 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; in intel_hdmi_compute_avi_infoframe()
760 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_avi_infoframe()
771 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_compute_spd_infoframe()
772 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; in intel_hdmi_compute_spd_infoframe()
775 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
778 crtc_state->infoframes.enable |= in intel_hdmi_compute_spd_infoframe()
786 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
789 frame->sdi = HDMI_SPD_SDI_PC; in intel_hdmi_compute_spd_infoframe()
792 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
804 &crtc_state->infoframes.hdmi.vendor.hdmi; in intel_hdmi_compute_hdmi_infoframe()
806 &conn_state->connector->display_info; in intel_hdmi_compute_hdmi_infoframe()
809 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) in intel_hdmi_compute_hdmi_infoframe()
812 crtc_state->infoframes.enable |= in intel_hdmi_compute_hdmi_infoframe()
816 conn_state->connector, in intel_hdmi_compute_hdmi_infoframe()
817 &crtc_state->hw.adjusted_mode); in intel_hdmi_compute_hdmi_infoframe()
818 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
822 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
834 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; in intel_hdmi_compute_drm_infoframe()
840 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
843 if (!conn_state->hdr_output_metadata) in intel_hdmi_compute_drm_infoframe()
846 crtc_state->infoframes.enable |= in intel_hdmi_compute_drm_infoframe()
851 drm_dbg_kms(display->drm, in intel_hdmi_compute_drm_infoframe()
857 if (drm_WARN_ON(display->drm, ret)) in intel_hdmi_compute_drm_infoframe()
870 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in g4x_set_infoframes()
873 u32 port = VIDEO_DIP_PORT(encoder->port); in g4x_set_infoframes()
892 drm_dbg_kms(display->drm, in g4x_set_infoframes()
906 drm_dbg_kms(display->drm, in g4x_set_infoframes()
924 &crtc_state->infoframes.avi); in g4x_set_infoframes()
927 &crtc_state->infoframes.spd); in g4x_set_infoframes()
930 &crtc_state->infoframes.hdmi); in g4x_set_infoframes()
936 * From HDMI specification 1.4a:
937 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
938 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
939 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
940 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
966 return mode->crtc_hdisplay % pixels_per_group == 0 && in gcp_default_phase_possible()
967 mode->crtc_htotal % pixels_per_group == 0 && in gcp_default_phase_possible()
968 mode->crtc_hblank_start % pixels_per_group == 0 && in gcp_default_phase_possible()
969 mode->crtc_hblank_end % pixels_per_group == 0 && in gcp_default_phase_possible()
970 mode->crtc_hsync_start % pixels_per_group == 0 && in gcp_default_phase_possible()
971 mode->crtc_hsync_end % pixels_per_group == 0 && in gcp_default_phase_possible()
972 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || in gcp_default_phase_possible()
973 mode->crtc_htotal/2 % pixels_per_group == 0); in gcp_default_phase_possible()
981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_set_gcp_infoframe()
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_set_gcp_infoframe()
985 if ((crtc_state->infoframes.enable & in intel_hdmi_set_gcp_infoframe()
990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
992 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
994 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
998 intel_de_write(display, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_read_gcp_infoframe()
1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_read_gcp_infoframe()
1011 if ((crtc_state->infoframes.enable & in intel_hdmi_read_gcp_infoframe()
1016 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1018 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1020 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1024 crtc_state->infoframes.gcp = intel_de_read(display, reg); in intel_hdmi_read_gcp_infoframe()
1031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_gcp_infoframe()
1033 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) in intel_hdmi_compute_gcp_infoframe()
1036 crtc_state->infoframes.enable |= in intel_hdmi_compute_gcp_infoframe()
1040 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1041 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; in intel_hdmi_compute_gcp_infoframe()
1044 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1045 &crtc_state->hw.adjusted_mode)) in intel_hdmi_compute_gcp_infoframe()
1046 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; in intel_hdmi_compute_gcp_infoframe()
1055 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_set_infoframes()
1057 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in ibx_set_infoframes()
1058 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_set_infoframes()
1060 u32 port = VIDEO_DIP_PORT(encoder->port); in ibx_set_infoframes()
1079 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
1099 &crtc_state->infoframes.avi); in ibx_set_infoframes()
1102 &crtc_state->infoframes.spd); in ibx_set_infoframes()
1105 &crtc_state->infoframes.hdmi); in ibx_set_infoframes()
1114 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_set_infoframes()
1116 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_set_infoframes()
1148 &crtc_state->infoframes.avi); in cpt_set_infoframes()
1151 &crtc_state->infoframes.spd); in cpt_set_infoframes()
1154 &crtc_state->infoframes.hdmi); in cpt_set_infoframes()
1163 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_set_infoframes()
1165 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_set_infoframes()
1167 u32 port = VIDEO_DIP_PORT(encoder->port); in vlv_set_infoframes()
1186 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
1206 &crtc_state->infoframes.avi); in vlv_set_infoframes()
1209 &crtc_state->infoframes.spd); in vlv_set_infoframes()
1212 &crtc_state->infoframes.hdmi); in vlv_set_infoframes()
1221 crtc_state->cpu_transcoder); in intel_hdmi_fastset_infoframes()
1224 if ((crtc_state->infoframes.enable & in intel_hdmi_fastset_infoframes()
1236 &crtc_state->infoframes.drm); in intel_hdmi_fastset_infoframes()
1246 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1250 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1271 &crtc_state->infoframes.avi); in hsw_set_infoframes()
1274 &crtc_state->infoframes.spd); in hsw_set_infoframes()
1277 &crtc_state->infoframes.hdmi); in hsw_set_infoframes()
1280 &crtc_state->infoframes.drm); in hsw_set_infoframes()
1283 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) in intel_dp_dual_mode_set_tmds_output() argument
1285 struct intel_display *display = to_intel_display(hdmi); in intel_dp_dual_mode_set_tmds_output()
1286 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_dp_dual_mode_set_tmds_output()
1288 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) in intel_dp_dual_mode_set_tmds_output()
1291 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", in intel_dp_dual_mode_set_tmds_output()
1294 drm_dp_dual_mode_set_tmds_output(display->drm, in intel_dp_dual_mode_set_tmds_output()
1295 hdmi->dp_dual_mode.type, ddc, enable); in intel_dp_dual_mode_set_tmds_output()
1301 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_read() local
1302 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_read()
1322 return ret >= 0 ? -EIO : ret; in intel_hdmi_hdcp_read()
1328 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write() local
1329 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_write()
1336 return -ENOMEM; in intel_hdmi_hdcp_write()
1350 ret = -EIO; in intel_hdmi_hdcp_write()
1361 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write_an_aksv() local
1362 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_write_an_aksv()
1368 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", in intel_hdmi_hdcp_write_an_aksv()
1375 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); in intel_hdmi_hdcp_write_an_aksv()
1390 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bksv()
1405 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_bstatus()
1421 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_repeater_present()
1439 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ri_prime()
1454 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ksv_ready()
1471 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_ksv_fifo()
1486 return -EINVAL; in intel_hdmi_hdcp_read_v_prime_part()
1491 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_v_prime_part()
1497 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, in kbl_repositioning_enc_en_signal() argument
1500 struct intel_display *display = to_intel_display(connector); in kbl_repositioning_enc_en_signal()
1501 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in kbl_repositioning_enc_en_signal()
1502 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); in kbl_repositioning_enc_en_signal()
1508 PIPEDSL(display, crtc->pipe)); in kbl_repositioning_enc_en_signal()
1514 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1517 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1522 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1525 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1539 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_toggle_signalling() local
1540 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_hdcp_toggle_signalling() local
1541 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in intel_hdmi_hdcp_toggle_signalling()
1547 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, in intel_hdmi_hdcp_toggle_signalling()
1551 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", in intel_hdmi_hdcp_toggle_signalling()
1561 return kbl_repositioning_enc_en_signal(connector, in intel_hdmi_hdcp_toggle_signalling()
1569 struct intel_connector *connector) in intel_hdmi_hdcp_check_link_once() argument
1572 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_check_link_once()
1573 enum port port = dig_port->base.port; in intel_hdmi_hdcp_check_link_once()
1574 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; in intel_hdmi_hdcp_check_link_once()
1591 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", in intel_hdmi_hdcp_check_link_once()
1601 struct intel_connector *connector) in intel_hdmi_hdcp_check_link() argument
1606 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) in intel_hdmi_hdcp_check_link()
1651 return -EINVAL; in get_hdcp2_msg_timeout()
1665 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", in hdcp2_detect_msg_availability()
1701 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_wait_for_msg()
1709 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, in intel_hdmi_hdcp2_write_msg() argument
1712 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_hdmi_hdcp2_write_msg()
1720 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, in intel_hdmi_hdcp2_read_msg() argument
1723 struct intel_display *display = to_intel_display(connector); in intel_hdmi_hdcp2_read_msg()
1724 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_hdmi_hdcp2_read_msg()
1725 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp2_read_msg() local
1726 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; in intel_hdmi_hdcp2_read_msg()
1731 hdcp->is_paired); in intel_hdmi_hdcp2_read_msg()
1740 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_read_msg()
1743 return -EINVAL; in intel_hdmi_hdcp2_read_msg()
1749 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", in intel_hdmi_hdcp2_read_msg()
1757 struct intel_connector *connector) in intel_hdmi_hdcp2_check_link() argument
1767 * Re-auth request and Link Integrity Failures are represented by in intel_hdmi_hdcp2_check_link()
1779 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, in intel_hdmi_hdcp2_get_capability() argument
1782 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_hdmi_hdcp2_get_capability()
1816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_source_max_tmds_clock()
1830 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); in intel_hdmi_source_max_tmds_clock()
1837 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, in intel_has_hdmi_sink() argument
1840 struct intel_connector *connector = hdmi->attached_connector; in intel_has_hdmi_sink() local
1842 return connector->base.display_info.is_hdmi && in intel_has_hdmi_sink()
1843 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; in intel_has_hdmi_sink()
1848 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_is_ycbcr420()
1851 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, in hdmi_port_clock_limit() argument
1855 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in hdmi_port_clock_limit()
1859 struct intel_connector *connector = hdmi->attached_connector; in hdmi_port_clock_limit() local
1860 const struct drm_display_info *info = &connector->base.display_info; in hdmi_port_clock_limit()
1862 if (hdmi->dp_dual_mode.max_tmds_clock) in hdmi_port_clock_limit()
1864 hdmi->dp_dual_mode.max_tmds_clock); in hdmi_port_clock_limit()
1866 if (info->max_tmds_clock) in hdmi_port_clock_limit()
1868 info->max_tmds_clock); in hdmi_port_clock_limit()
1877 hdmi_port_clock_valid(struct intel_hdmi *hdmi, in hdmi_port_clock_valid() argument
1881 struct intel_display *display = to_intel_display(hdmi); in hdmi_port_clock_valid()
1882 struct drm_i915_private *dev_priv = to_i915(display->drm); in hdmi_port_clock_valid()
1883 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in hdmi_port_clock_valid()
1887 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, in hdmi_port_clock_valid()
1891 /* GLK DPLL can't generate 446-480 MHz */ in hdmi_port_clock_valid()
1895 /* BXT/GLK DPLL can't generate 223-240 MHz */ in hdmi_port_clock_valid()
1900 /* CHV DPLL can't generate 216-240 MHz */ in hdmi_port_clock_valid()
1904 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ in hdmi_port_clock_valid()
1908 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ in hdmi_port_clock_valid()
1913 * SNPS PHYs' MPLLB table-based programming can only handle a fixed in hdmi_port_clock_valid()
1917 * the MPLLB for HDMI in the future. in hdmi_port_clock_valid()
1920 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); in hdmi_port_clock_valid()
1957 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, in intel_hdmi_sink_bpc_possible() argument
1961 const struct drm_display_info *info = &connector->display_info; in intel_hdmi_sink_bpc_possible()
1962 const struct drm_hdmi_info *hdmi = &info->hdmi; in intel_hdmi_sink_bpc_possible() local
1970 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; in intel_hdmi_sink_bpc_possible()
1972 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; in intel_hdmi_sink_bpc_possible()
1978 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; in intel_hdmi_sink_bpc_possible()
1980 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; in intel_hdmi_sink_bpc_possible()
1990 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, in intel_hdmi_mode_clock_valid() argument
1994 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_clock_valid()
1995 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_mode_clock_valid() local
2004 for (bpc = 12; bpc >= 8; bpc -= 2) { in intel_hdmi_mode_clock_valid()
2010 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) in intel_hdmi_mode_clock_valid()
2013 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); in intel_hdmi_mode_clock_valid()
2019 drm_WARN_ON(display->drm, status == MODE_OK); in intel_hdmi_mode_clock_valid()
2025 intel_hdmi_mode_valid(struct drm_connector *connector, in intel_hdmi_mode_valid() argument
2028 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_valid()
2029 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_mode_valid() local
2030 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_hdmi_mode_valid()
2032 int clock = mode->clock; in intel_hdmi_mode_valid()
2033 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_hdmi_mode_valid()
2034 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); in intel_hdmi_mode_valid()
2042 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) in intel_hdmi_mode_valid()
2048 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { in intel_hdmi_mode_valid()
2063 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); in intel_hdmi_mode_valid()
2070 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); in intel_hdmi_mode_valid()
2073 !connector->ycbcr_420_allowed || in intel_hdmi_mode_valid()
2074 !drm_mode_is_420_also(&connector->display_info, mode)) in intel_hdmi_mode_valid()
2078 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); in intel_hdmi_mode_valid()
2089 struct drm_atomic_state *state = crtc_state->uapi.state; in intel_hdmi_bpc_possible()
2091 struct drm_connector *connector; in intel_hdmi_bpc_possible() local
2094 for_each_new_connector_in_state(state, connector, connector_state, i) { in intel_hdmi_bpc_possible()
2095 if (connector_state->crtc != crtc_state->uapi.crtc) in intel_hdmi_bpc_possible()
2098 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, in intel_hdmi_bpc_possible()
2099 crtc_state->sink_format)) in intel_hdmi_bpc_possible()
2110 &crtc_state->hw.adjusted_mode; in hdmi_bpc_possible()
2118 (adjusted_mode->crtc_hblank_end - in hdmi_bpc_possible()
2119 adjusted_mode->crtc_hblank_start) % 8 == 2) in hdmi_bpc_possible()
2122 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); in hdmi_bpc_possible()
2134 * bandwidth constraints. HDMI minimum is 8bpc however. in intel_hdmi_compute_bpc()
2136 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2146 for (; bpc >= 8; bpc -= 2) { in intel_hdmi_compute_bpc()
2148 crtc_state->sink_format); in intel_hdmi_compute_bpc()
2153 crtc_state->has_hdmi_sink) == MODE_OK) in intel_hdmi_compute_bpc()
2157 return -EINVAL; in intel_hdmi_compute_bpc()
2166 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_clock()
2167 int bpc, clock = adjusted_mode->crtc_clock; in intel_hdmi_compute_clock()
2169 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_clock()
2177 crtc_state->port_clock = in intel_hdmi_compute_clock()
2178 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); in intel_hdmi_compute_clock()
2183 * back up to the HDMI minimum 8bpc in that case. in intel_hdmi_compute_clock()
2185 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2187 drm_dbg_kms(display->drm, in intel_hdmi_compute_clock()
2188 "picking %d bpc for HDMI output (pipe bpp: %d)\n", in intel_hdmi_compute_clock()
2189 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
2200 &crtc_state->hw.adjusted_mode; in intel_hdmi_limited_color_range()
2204 * crtc_state->limited_color_range only applies to RGB, in intel_hdmi_limited_color_range()
2209 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_limited_color_range()
2212 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { in intel_hdmi_limited_color_range()
2213 /* See CEA-861-E - 5.1 Default Encoding Parameters */ in intel_hdmi_limited_color_range()
2214 return crtc_state->has_hdmi_sink && in intel_hdmi_limited_color_range()
2218 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; in intel_hdmi_limited_color_range()
2226 struct drm_connector *connector = conn_state->connector; in intel_hdmi_has_audio() local
2230 if (!crtc_state->has_hdmi_sink) in intel_hdmi_has_audio()
2233 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) in intel_hdmi_has_audio()
2234 return connector->display_info.has_audio; in intel_hdmi_has_audio()
2236 return intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_hdmi_has_audio()
2241 struct intel_connector *connector, in intel_hdmi_sink_format() argument
2244 if (!crtc_state->has_hdmi_sink) in intel_hdmi_sink_format()
2247 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) in intel_hdmi_sink_format()
2256 return crtc_state->sink_format; in intel_hdmi_output_format()
2265 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_hdmi_compute_output_format() local
2266 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_output_format()
2267 const struct drm_display_info *info = &connector->base.display_info; in intel_hdmi_compute_output_format()
2271 crtc_state->sink_format = in intel_hdmi_compute_output_format()
2272 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); in intel_hdmi_compute_output_format()
2274 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_hdmi_compute_output_format()
2275 drm_dbg_kms(display->drm, in intel_hdmi_compute_output_format()
2277 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_output_format()
2280 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
2283 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in intel_hdmi_compute_output_format()
2284 !crtc_state->has_hdmi_sink || in intel_hdmi_compute_output_format()
2285 !connector->base.ycbcr_420_allowed || in intel_hdmi_compute_output_format()
2289 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_compute_output_format()
2290 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
2299 return crtc_state->uapi.encoder_mask && in intel_hdmi_is_cloned()
2300 !is_power_of_2(crtc_state->uapi.encoder_mask); in intel_hdmi_is_cloned()
2306 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and in source_supports_scrambling()
2309 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is in source_supports_scrambling()
2314 * HDMI 1.4 retimer chip doesn't. in source_supports_scrambling()
2326 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); in intel_hdmi_compute_has_hdmi_sink() local
2328 return intel_has_hdmi_sink(hdmi, conn_state) && in intel_hdmi_compute_has_hdmi_sink()
2337 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_hdmi_compute_config()
2338 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_config() local
2339 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; in intel_hdmi_compute_config()
2342 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_hdmi_compute_config()
2343 return -EINVAL; in intel_hdmi_compute_config()
2345 if (!connector->interlace_allowed && in intel_hdmi_compute_config()
2346 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_hdmi_compute_config()
2347 return -EINVAL; in intel_hdmi_compute_config()
2349 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_config()
2351 if (pipe_config->has_hdmi_sink) in intel_hdmi_compute_config()
2352 pipe_config->has_infoframe = true; in intel_hdmi_compute_config()
2354 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_config()
2355 pipe_config->pixel_multiplier = 2; in intel_hdmi_compute_config()
2357 pipe_config->has_audio = in intel_hdmi_compute_config()
2369 drm_dbg_kms(display->drm, in intel_hdmi_compute_config()
2370 "unsupported HDMI clock (%d kHz), rejecting mode\n", in intel_hdmi_compute_config()
2371 pipe_config->hw.adjusted_mode.crtc_clock); in intel_hdmi_compute_config()
2381 pipe_config->limited_color_range = in intel_hdmi_compute_config()
2384 if (conn_state->picture_aspect_ratio) in intel_hdmi_compute_config()
2385 adjusted_mode->picture_aspect_ratio = in intel_hdmi_compute_config()
2386 conn_state->picture_aspect_ratio; in intel_hdmi_compute_config()
2388 pipe_config->lane_count = 4; in intel_hdmi_compute_config()
2390 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { in intel_hdmi_compute_config()
2391 if (scdc->scrambling.low_rates) in intel_hdmi_compute_config()
2392 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2394 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
2395 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2396 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_hdmi_compute_config()
2404 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); in intel_hdmi_compute_config()
2405 return -EINVAL; in intel_hdmi_compute_config()
2409 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); in intel_hdmi_compute_config()
2410 return -EINVAL; in intel_hdmi_compute_config()
2414 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); in intel_hdmi_compute_config()
2415 return -EINVAL; in intel_hdmi_compute_config()
2419 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); in intel_hdmi_compute_config()
2420 return -EINVAL; in intel_hdmi_compute_config()
2438 intel_hdmi_unset_edid(struct drm_connector *connector) in intel_hdmi_unset_edid() argument
2440 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_unset_edid()
2442 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; in intel_hdmi_unset_edid()
2443 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_unset_edid()
2445 drm_edid_free(to_intel_connector(connector)->detect_edid); in intel_hdmi_unset_edid()
2446 to_intel_connector(connector)->detect_edid = NULL; in intel_hdmi_unset_edid()
2450 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) in intel_hdmi_dp_dual_mode_detect() argument
2452 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_dp_dual_mode_detect()
2453 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_dp_dual_mode_detect()
2454 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_dp_dual_mode_detect() local
2455 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in intel_hdmi_dp_dual_mode_detect()
2456 struct i2c_adapter *ddc = connector->ddc; in intel_hdmi_dp_dual_mode_detect()
2459 type = drm_dp_dual_mode_detect(display->drm, ddc); in intel_hdmi_dp_dual_mode_detect()
2471 if (!connector->force && in intel_hdmi_dp_dual_mode_detect()
2472 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { in intel_hdmi_dp_dual_mode_detect()
2473 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2484 hdmi->dp_dual_mode.type = type; in intel_hdmi_dp_dual_mode_detect()
2485 hdmi->dp_dual_mode.max_tmds_clock = in intel_hdmi_dp_dual_mode_detect()
2486 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); in intel_hdmi_dp_dual_mode_detect()
2488 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2491 hdmi->dp_dual_mode.max_tmds_clock); in intel_hdmi_dp_dual_mode_detect()
2495 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { in intel_hdmi_dp_dual_mode_detect()
2496 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2497 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); in intel_hdmi_dp_dual_mode_detect()
2498 hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_dp_dual_mode_detect()
2503 intel_hdmi_set_edid(struct drm_connector *connector) in intel_hdmi_set_edid() argument
2505 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_set_edid()
2506 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_set_edid()
2507 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_set_edid()
2508 struct i2c_adapter *ddc = connector->ddc; in intel_hdmi_set_edid()
2515 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_hdmi_set_edid()
2518 drm_dbg_kms(display->drm, in intel_hdmi_set_edid()
2519 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_hdmi_set_edid()
2521 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_hdmi_set_edid()
2526 drm_edid_connector_update(connector, drm_edid); in intel_hdmi_set_edid()
2528 to_intel_connector(connector)->detect_edid = drm_edid; in intel_hdmi_set_edid()
2531 intel_hdmi_dp_dual_mode_detect(connector); in intel_hdmi_set_edid()
2538 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, in intel_hdmi_set_edid()
2539 connector->display_info.source_physical_address); in intel_hdmi_set_edid()
2545 intel_hdmi_detect(struct drm_connector *connector, bool force) in intel_hdmi_detect() argument
2547 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_detect()
2549 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_detect()
2550 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_detect()
2551 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; in intel_hdmi_detect()
2554 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_detect()
2555 connector->base.id, connector->name); in intel_hdmi_detect()
2561 return connector->status; in intel_hdmi_detect()
2569 intel_hdmi_unset_edid(connector); in intel_hdmi_detect()
2571 if (intel_hdmi_set_edid(connector)) in intel_hdmi_detect()
2578 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); in intel_hdmi_detect()
2584 intel_hdmi_force(struct drm_connector *connector) in intel_hdmi_force() argument
2586 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_force()
2588 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_force()
2589 connector->base.id, connector->name); in intel_hdmi_force()
2594 intel_hdmi_unset_edid(connector); in intel_hdmi_force()
2596 if (connector->status != connector_status_connected) in intel_hdmi_force()
2599 intel_hdmi_set_edid(connector); in intel_hdmi_force()
2602 static int intel_hdmi_get_modes(struct drm_connector *connector) in intel_hdmi_get_modes() argument
2604 /* drm_edid_connector_update() done in ->detect() or ->force() */ in intel_hdmi_get_modes()
2605 return drm_edid_connector_add_modes(connector); in intel_hdmi_get_modes()
2609 intel_hdmi_connector_register(struct drm_connector *connector) in intel_hdmi_connector_register() argument
2613 ret = intel_connector_register(connector); in intel_hdmi_connector_register()
2620 static void intel_hdmi_connector_unregister(struct drm_connector *connector) in intel_hdmi_connector_unregister() argument
2622 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; in intel_hdmi_connector_unregister()
2626 intel_connector_unregister(connector); in intel_hdmi_connector_unregister()
2642 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, in intel_hdmi_connector_atomic_check() argument
2645 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_connector_atomic_check()
2648 return intel_digital_connector_atomic_check(connector, state); in intel_hdmi_connector_atomic_check()
2650 return g4x_hdmi_connector_atomic_check(connector, state); in intel_hdmi_connector_atomic_check()
2660 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) in intel_hdmi_add_properties() argument
2664 intel_attach_force_audio_property(connector); in intel_hdmi_add_properties()
2665 intel_attach_broadcast_rgb_property(connector); in intel_hdmi_add_properties()
2666 intel_attach_aspect_ratio_property(connector); in intel_hdmi_add_properties()
2668 intel_attach_hdmi_colorspace_property(connector); in intel_hdmi_add_properties()
2669 drm_connector_attach_content_type_property(connector); in intel_hdmi_add_properties()
2672 drm_connector_attach_hdr_output_metadata_property(connector); in intel_hdmi_add_properties()
2675 drm_connector_attach_max_bpc_property(connector, 8, 12); in intel_hdmi_add_properties()
2681 * @connector: drm_connector
2687 * This function handles scrambling on HDMI 2.0 capable sinks.
2689 * it enables scrambling. This should be called before enabling the HDMI
2697 struct drm_connector *connector, in intel_hdmi_handle_sink_scrambling() argument
2703 &connector->display_info.hdmi.scdc.scrambling; in intel_hdmi_handle_sink_scrambling()
2705 if (!sink_scrambling->supported) in intel_hdmi_handle_sink_scrambling()
2708 drm_dbg_kms(display->drm, in intel_hdmi_handle_sink_scrambling()
2709 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", in intel_hdmi_handle_sink_scrambling()
2710 connector->base.id, connector->name, in intel_hdmi_handle_sink_scrambling()
2714 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && in intel_hdmi_handle_sink_scrambling()
2715 drm_scdc_set_scrambling(connector, scrambling); in intel_hdmi_handle_sink_scrambling()
2720 enum port port = encoder->port; in chv_encoder_to_ddc_pin()
2743 enum port port = encoder->port; in bxt_encoder_to_ddc_pin()
2763 enum port port = encoder->port; in cnp_encoder_to_ddc_pin()
2790 enum port port = encoder->port; in icl_encoder_to_ddc_pin()
2797 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); in icl_encoder_to_ddc_pin()
2826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in rkl_encoder_to_ddc_pin()
2829 WARN_ON(encoder->port == PORT_C); in rkl_encoder_to_ddc_pin()
2833 * final two outputs use type-c pins, even though they're actually in rkl_encoder_to_ddc_pin()
2834 * combo outputs. With CMP, the traditional DDI A-D pins are used for in rkl_encoder_to_ddc_pin()
2838 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in rkl_encoder_to_ddc_pin()
2846 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen9bc_tgp_encoder_to_ddc_pin()
2849 drm_WARN_ON(display->drm, encoder->port == PORT_A); in gen9bc_tgp_encoder_to_ddc_pin()
2853 * final two outputs use type-c pins, even though they're actually in gen9bc_tgp_encoder_to_ddc_pin()
2854 * combo outputs. With CMP, the traditional DDI A-D pins are used for in gen9bc_tgp_encoder_to_ddc_pin()
2858 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in gen9bc_tgp_encoder_to_ddc_pin()
2872 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); in adls_encoder_to_ddc_pin()
2875 * Pin mapping for ADL-S requires TC pins for all combo phy outputs in adls_encoder_to_ddc_pin()
2881 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; in adls_encoder_to_ddc_pin()
2886 enum port port = encoder->port; in g4x_encoder_to_ddc_pin()
2910 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_default_ddc_pin()
2944 for_each_intel_encoder(display->drm, other) { in get_encoder_by_ddc_pin()
2945 struct intel_connector *connector; in get_encoder_by_ddc_pin() local
2953 connector = enc_to_dig_port(other)->hdmi.attached_connector; in get_encoder_by_ddc_pin()
2955 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) in get_encoder_by_ddc_pin()
2969 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); in intel_hdmi_ddc_pin()
2978 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2980 encoder->base.base.id, encoder->base.name, ddc_pin); in intel_hdmi_ddc_pin()
2986 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2988 encoder->base.base.id, encoder->base.name, ddc_pin, in intel_hdmi_ddc_pin()
2989 other->base.base.id, other->base.name); in intel_hdmi_ddc_pin()
2993 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2995 encoder->base.base.id, encoder->base.name, in intel_hdmi_ddc_pin()
3005 to_i915(dig_port->base.base.dev); in intel_infoframe_init()
3008 dig_port->write_infoframe = vlv_write_infoframe; in intel_infoframe_init()
3009 dig_port->read_infoframe = vlv_read_infoframe; in intel_infoframe_init()
3010 dig_port->set_infoframes = vlv_set_infoframes; in intel_infoframe_init()
3011 dig_port->infoframes_enabled = vlv_infoframes_enabled; in intel_infoframe_init()
3013 dig_port->write_infoframe = g4x_write_infoframe; in intel_infoframe_init()
3014 dig_port->read_infoframe = g4x_read_infoframe; in intel_infoframe_init()
3015 dig_port->set_infoframes = g4x_set_infoframes; in intel_infoframe_init()
3016 dig_port->infoframes_enabled = g4x_infoframes_enabled; in intel_infoframe_init()
3018 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { in intel_infoframe_init()
3019 dig_port->write_infoframe = lspcon_write_infoframe; in intel_infoframe_init()
3020 dig_port->read_infoframe = lspcon_read_infoframe; in intel_infoframe_init()
3021 dig_port->set_infoframes = lspcon_set_infoframes; in intel_infoframe_init()
3022 dig_port->infoframes_enabled = lspcon_infoframes_enabled; in intel_infoframe_init()
3024 dig_port->write_infoframe = hsw_write_infoframe; in intel_infoframe_init()
3025 dig_port->read_infoframe = hsw_read_infoframe; in intel_infoframe_init()
3026 dig_port->set_infoframes = hsw_set_infoframes; in intel_infoframe_init()
3027 dig_port->infoframes_enabled = hsw_infoframes_enabled; in intel_infoframe_init()
3030 dig_port->write_infoframe = ibx_write_infoframe; in intel_infoframe_init()
3031 dig_port->read_infoframe = ibx_read_infoframe; in intel_infoframe_init()
3032 dig_port->set_infoframes = ibx_set_infoframes; in intel_infoframe_init()
3033 dig_port->infoframes_enabled = ibx_infoframes_enabled; in intel_infoframe_init()
3035 dig_port->write_infoframe = cpt_write_infoframe; in intel_infoframe_init()
3036 dig_port->read_infoframe = cpt_read_infoframe; in intel_infoframe_init()
3037 dig_port->set_infoframes = cpt_set_infoframes; in intel_infoframe_init()
3038 dig_port->infoframes_enabled = cpt_infoframes_enabled; in intel_infoframe_init()
3046 struct drm_connector *connector = &intel_connector->base; in intel_hdmi_init_connector() local
3047 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_hdmi_init_connector()
3048 struct intel_encoder *intel_encoder = &dig_port->base; in intel_hdmi_init_connector()
3049 struct drm_device *dev = intel_encoder->base.dev; in intel_hdmi_init_connector()
3050 enum port port = intel_encoder->port; in intel_hdmi_init_connector()
3054 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3055 "Adding HDMI connector on [ENCODER:%d:%s]\n", in intel_hdmi_init_connector()
3056 intel_encoder->base.base.id, intel_encoder->base.name); in intel_hdmi_init_connector()
3061 if (drm_WARN(dev, dig_port->max_lanes < 4, in intel_hdmi_init_connector()
3062 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", in intel_hdmi_init_connector()
3063 dig_port->max_lanes, intel_encoder->base.base.id, in intel_hdmi_init_connector()
3064 intel_encoder->base.name)) in intel_hdmi_init_connector()
3071 drm_connector_init_with_ddc(dev, connector, in intel_hdmi_init_connector()
3076 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); in intel_hdmi_init_connector()
3079 connector->interlace_allowed = true; in intel_hdmi_init_connector()
3081 connector->stereo_allowed = true; in intel_hdmi_init_connector()
3084 connector->ycbcr_420_allowed = true; in intel_hdmi_init_connector()
3086 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_hdmi_init_connector()
3087 intel_connector->base.polled = intel_connector->polled; in intel_hdmi_init_connector()
3090 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; in intel_hdmi_init_connector()
3092 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_hdmi_init_connector()
3094 intel_hdmi_add_properties(intel_hdmi, connector); in intel_hdmi_init_connector()
3097 intel_hdmi->attached_connector = intel_connector; in intel_hdmi_init_connector()
3103 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3107 cec_fill_conn_info_from_drm(&conn_info, connector); in intel_hdmi_init_connector()
3109 intel_hdmi->cec_notifier = in intel_hdmi_init_connector()
3110 cec_notifier_conn_register(dev->dev, port_identifier(port), in intel_hdmi_init_connector()
3112 if (!intel_hdmi->cec_notifier) in intel_hdmi_init_connector()
3113 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); in intel_hdmi_init_connector()
3119 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3143 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3150 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3178 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_hdmi_dsc_get_num_slices()
3189 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || in intel_hdmi_dsc_get_num_slices()
3190 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_dsc_get_num_slices()
3213 * clock per slice (in MHz) as read from HF-VSDB. in intel_hdmi_dsc_get_num_slices()
3225 * of PCON encoder and HDMI decoder can support. in intel_hdmi_dsc_get_num_slices()
3245 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); in intel_hdmi_dsc_get_num_slices()
3254 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3283 * for each bpp we check if no of bytes can be supported by HDMI sink in intel_hdmi_dsc_get_bpp()
3332 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()
3343 bpp_target_x16 -= bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()