Lines Matching +full:db4 +full:- +full:db7
3 * Copyright © 2006-2009 Intel Corporation
44 #include <media/cec-notifier.h>
77 drm_WARN(display->drm,
78 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,
86 drm_WARN(display->drm,
220 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
271 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
286 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
290 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
301 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
307 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
327 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
331 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
338 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
345 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
361 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
365 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
379 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
385 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);
401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
405 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
409 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
439 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
477 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),
482 VLV_TVIDEO_DIP_DATA(crtc->pipe));
489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
518 drm_WARN_ON(display->drm, len > data_size);
536 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
537 !crtc_state->has_panel_replay && type == DP_SDP_VSC))
552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
566 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
613 val = dig_port->infoframes_enabled(encoder, crtc_state);
639 * DW2: DB7 | DB6 | DB5 | DB4
657 if ((crtc_state->infoframes.enable &
661 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
665 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
666 if (drm_WARN_ON(encoder->base.dev, len < 0))
674 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
686 if ((crtc_state->infoframes.enable &
690 dig_port->read_infoframe(encoder, crtc_state,
697 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
699 drm_dbg_kms(encoder->base.dev,
704 if (frame->any.type != type)
705 drm_dbg_kms(encoder->base.dev,
707 frame->any.type, type);
715 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
717 &crtc_state->hw.adjusted_mode;
718 struct intel_connector *connector = to_intel_connector(conn_state->connector);
721 if (!crtc_state->has_infoframe)
724 crtc_state->infoframes.enable |=
727 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base,
732 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
733 frame->colorspace = HDMI_COLORSPACE_YUV420;
734 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
735 frame->colorspace = HDMI_COLORSPACE_YUV444;
737 frame->colorspace = HDMI_COLORSPACE_RGB;
742 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
743 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
745 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
746 drm_hdmi_avi_infoframe_quant_range(frame, &connector->base,
748 crtc_state->limited_color_range ?
752 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
753 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
761 if (drm_WARN_ON(encoder->base.dev, ret))
773 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
776 if (!crtc_state->has_infoframe)
779 crtc_state->infoframes.enable |=
782 if (display->platform.dgfx)
787 if (drm_WARN_ON(encoder->base.dev, ret))
790 frame->sdi = HDMI_SPD_SDI_PC;
793 if (drm_WARN_ON(encoder->base.dev, ret))
805 &crtc_state->infoframes.hdmi.vendor.hdmi;
807 &conn_state->connector->display_info;
810 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
813 crtc_state->infoframes.enable |=
817 conn_state->connector,
818 &crtc_state->hw.adjusted_mode);
819 if (drm_WARN_ON(encoder->base.dev, ret))
823 if (drm_WARN_ON(encoder->base.dev, ret))
835 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
841 if (!crtc_state->has_infoframe)
844 if (!conn_state->hdr_output_metadata)
847 crtc_state->infoframes.enable |=
852 drm_dbg_kms(display->drm,
858 if (drm_WARN_ON(display->drm, ret))
871 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
874 u32 port = VIDEO_DIP_PORT(encoder->port);
893 drm_dbg_kms(display->drm,
907 drm_dbg_kms(display->drm,
925 &crtc_state->infoframes.avi);
928 &crtc_state->infoframes.spd);
931 &crtc_state->infoframes.hdmi);
938 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
939 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
940 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
941 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
967 return mode->crtc_hdisplay % pixels_per_group == 0 &&
968 mode->crtc_htotal % pixels_per_group == 0 &&
969 mode->crtc_hblank_start % pixels_per_group == 0 &&
970 mode->crtc_hblank_end % pixels_per_group == 0 &&
971 mode->crtc_hsync_start % pixels_per_group == 0 &&
972 mode->crtc_hsync_end % pixels_per_group == 0 &&
973 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
974 mode->crtc_htotal/2 % pixels_per_group == 0);
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
985 if ((crtc_state->infoframes.enable &
990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
991 else if (display->platform.valleyview || display->platform.cherryview)
992 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
994 reg = TVIDEO_DIP_GCP(crtc->pipe);
998 intel_de_write(display, reg, crtc_state->infoframes.gcp);
1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1010 if ((crtc_state->infoframes.enable &
1015 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
1016 else if (display->platform.valleyview || display->platform.cherryview)
1017 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1019 reg = TVIDEO_DIP_GCP(crtc->pipe);
1023 crtc_state->infoframes.gcp = intel_de_read(display, reg);
1032 if (display->platform.g4x || !crtc_state->has_infoframe)
1035 crtc_state->infoframes.enable |=
1039 if (crtc_state->pipe_bpp > 24)
1040 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1043 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1044 &crtc_state->hw.adjusted_mode))
1045 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1056 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1057 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1059 u32 port = VIDEO_DIP_PORT(encoder->port);
1078 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
1098 &crtc_state->infoframes.avi);
1101 &crtc_state->infoframes.spd);
1104 &crtc_state->infoframes.hdmi);
1113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1115 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1147 &crtc_state->infoframes.avi);
1150 &crtc_state->infoframes.spd);
1153 &crtc_state->infoframes.hdmi);
1162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1164 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1166 u32 port = VIDEO_DIP_PORT(encoder->port);
1185 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
1205 &crtc_state->infoframes.avi);
1208 &crtc_state->infoframes.spd);
1211 &crtc_state->infoframes.hdmi);
1220 crtc_state->cpu_transcoder);
1223 if ((crtc_state->infoframes.enable &
1235 &crtc_state->infoframes.drm);
1245 crtc_state->cpu_transcoder);
1249 crtc_state->cpu_transcoder);
1270 &crtc_state->infoframes.avi);
1273 &crtc_state->infoframes.spd);
1276 &crtc_state->infoframes.hdmi);
1279 &crtc_state->infoframes.drm);
1285 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1287 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1290 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",
1293 drm_dp_dual_mode_set_tmds_output(display->drm,
1294 hdmi->dp_dual_mode.type, ddc, enable);
1300 struct intel_hdmi *hdmi = &dig_port->hdmi;
1301 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1321 return ret >= 0 ? -EIO : ret;
1327 struct intel_hdmi *hdmi = &dig_port->hdmi;
1328 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1335 return -ENOMEM;
1349 ret = -EIO;
1360 struct intel_hdmi *hdmi = &dig_port->hdmi;
1361 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1367 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",
1374 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);
1389 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",
1404 drm_dbg_kms(display->drm,
1420 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
1438 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",
1453 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
1470 drm_dbg_kms(display->drm,
1485 return -EINVAL;
1490 drm_dbg_kms(display->drm,
1501 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1507 PIPEDSL(display, crtc->pipe));
1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1516 drm_err(display->drm,
1521 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1524 drm_err(display->drm,
1538 struct intel_hdmi *hdmi = &dig_port->hdmi;
1539 struct intel_connector *connector = hdmi->attached_connector;
1545 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1549 drm_err(display->drm, "%s HDCP signalling failed (%d)\n",
1558 if (display->platform.kabylake && enable)
1570 enum port port = dig_port->base.port;
1571 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1588 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
1648 return -EINVAL;
1662 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",
1698 drm_dbg_kms(display->drm,
1722 struct intel_hdmi *hdmi = &dig_port->hdmi;
1723 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1728 hdcp->is_paired);
1737 drm_dbg_kms(display->drm,
1740 return -EINVAL;
1746 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",
1764 * Re-auth request and Link Integrity Failures are represented by
1815 if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s)
1819 else if (DISPLAY_VER(display) >= 8 || display->platform.haswell)
1826 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1836 struct intel_connector *connector = hdmi->attached_connector;
1838 return connector->base.display_info.is_hdmi &&
1839 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1844 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1851 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1855 struct intel_connector *connector = hdmi->attached_connector;
1856 const struct drm_display_info *info = &connector->base.display_info;
1858 if (hdmi->dp_dual_mode.max_tmds_clock)
1860 hdmi->dp_dual_mode.max_tmds_clock);
1862 if (info->max_tmds_clock)
1864 info->max_tmds_clock);
1878 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1886 /* GLK DPLL can't generate 446-480 MHz */
1887 if (display->platform.geminilake && clock > 446666 && clock < 480000)
1890 /* BXT/GLK DPLL can't generate 223-240 MHz */
1891 if ((display->platform.geminilake || display->platform.broxton) &&
1895 /* CHV DPLL can't generate 216-240 MHz */
1896 if (display->platform.cherryview && clock > 216000 && clock < 240000)
1899 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1903 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1945 const struct drm_display_info *info = &connector->base.display_info;
1946 const struct drm_hdmi_info *hdmi = &info->hdmi;
1954 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1956 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1962 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1964 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1989 for (bpc = 12; bpc >= 8; bpc -= 2) {
1995 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink,
2005 drm_WARN_ON(display->drm, status == MODE_OK);
2018 int clock = mode->clock;
2019 int max_dotclk = display->cdclk.max_dotclk_freq;
2020 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state);
2028 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2034 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2049 ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode);
2056 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
2059 !connector->base.ycbcr_420_allowed ||
2060 !drm_mode_is_420_also(&connector->base.display_info, mode))
2064 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink,
2076 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
2082 if (connector_state->base.crtc != crtc_state->uapi.crtc)
2085 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink,
2086 crtc_state->sink_format))
2097 &crtc_state->hw.adjusted_mode;
2105 (adjusted_mode->crtc_hblank_end -
2106 adjusted_mode->crtc_hblank_start) % 8 == 2)
2109 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2123 bpc = max(crtc_state->pipe_bpp / 3, 8);
2133 for (; bpc >= 8; bpc -= 2) {
2135 crtc_state->sink_format);
2140 crtc_state->has_hdmi_sink) == MODE_OK)
2144 return -EINVAL;
2153 &crtc_state->hw.adjusted_mode;
2154 int bpc, clock = adjusted_mode->crtc_clock;
2156 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2164 crtc_state->port_clock =
2165 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2172 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2174 drm_dbg_kms(display->drm,
2176 bpc, crtc_state->pipe_bpp);
2187 &crtc_state->hw.adjusted_mode;
2191 * crtc_state->limited_color_range only applies to RGB,
2196 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2199 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2200 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2201 return crtc_state->has_hdmi_sink &&
2205 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2213 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2217 if (!crtc_state->has_hdmi_sink)
2220 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2221 return connector->base.display_info.has_audio;
2223 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2231 if (!crtc_state->has_hdmi_sink)
2234 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2243 return crtc_state->sink_format;
2252 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2253 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2254 const struct drm_display_info *info = &connector->base.display_info;
2258 crtc_state->sink_format =
2261 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2262 drm_dbg_kms(display->drm,
2264 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2267 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2270 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2271 !crtc_state->has_hdmi_sink ||
2272 !connector->base.ycbcr_420_allowed ||
2276 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2277 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2286 return crtc_state->uapi.encoder_mask &&
2287 !is_power_of_2(crtc_state->uapi.encoder_mask);
2324 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2325 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2326 struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc;
2329 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2330 return -EINVAL;
2332 if (!connector->base.interlace_allowed &&
2333 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2334 return -EINVAL;
2336 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2338 if (pipe_config->has_hdmi_sink)
2339 pipe_config->has_infoframe = true;
2341 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2342 pipe_config->pixel_multiplier = 2;
2344 pipe_config->has_audio =
2356 drm_dbg_kms(display->drm,
2358 pipe_config->hw.adjusted_mode.crtc_clock);
2368 pipe_config->limited_color_range =
2371 if (conn_state->picture_aspect_ratio)
2372 adjusted_mode->picture_aspect_ratio =
2373 conn_state->picture_aspect_ratio;
2375 pipe_config->lane_count = 4;
2377 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2378 if (scdc->scrambling.low_rates)
2379 pipe_config->hdmi_scrambling = true;
2381 if (pipe_config->port_clock > 340000) {
2382 pipe_config->hdmi_scrambling = true;
2383 pipe_config->hdmi_high_tmds_clock_ratio = true;
2393 drm_dbg_kms(display->drm, "bad AVI infoframe\n");
2394 return -EINVAL;
2398 drm_dbg_kms(display->drm, "bad SPD infoframe\n");
2399 return -EINVAL;
2403 drm_dbg_kms(display->drm, "bad HDMI infoframe\n");
2404 return -EINVAL;
2408 drm_dbg_kms(display->drm, "bad DRM infoframe\n");
2409 return -EINVAL;
2432 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2433 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2435 drm_edid_free(connector->detect_edid);
2436 connector->detect_edid = NULL;
2445 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2446 struct i2c_adapter *ddc = connector->base.ddc;
2449 type = drm_dp_dual_mode_detect(display->drm, ddc);
2461 if (!connector->base.force &&
2462 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2463 drm_dbg_kms(display->drm,
2474 hdmi->dp_dual_mode.type = type;
2475 hdmi->dp_dual_mode.max_tmds_clock =
2476 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);
2478 drm_dbg_kms(display->drm,
2481 hdmi->dp_dual_mode.max_tmds_clock);
2484 if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) &&
2485 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2486 drm_dbg_kms(display->drm,
2488 hdmi->dp_dual_mode.max_tmds_clock = 0;
2498 struct i2c_adapter *ddc = connector->base.ddc;
2505 drm_edid = drm_edid_read_ddc(&connector->base, ddc);
2508 drm_dbg_kms(display->drm,
2509 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2511 drm_edid = drm_edid_read_ddc(&connector->base, ddc);
2516 drm_edid_connector_update(&connector->base, drm_edid);
2518 connector->detect_edid = drm_edid;
2521 intel_hdmi_dp_dual_mode_detect(&connector->base);
2528 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier,
2529 connector->base.display_info.source_physical_address);
2541 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2544 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
2545 connector->base.base.id, connector->base.name);
2551 return connector->base.status;
2559 intel_hdmi_unset_edid(&connector->base);
2561 if (intel_hdmi_set_edid(&connector->base))
2568 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2579 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
2580 connector->base.base.id, connector->base.name);
2585 intel_hdmi_unset_edid(&connector->base);
2587 if (connector->base.status != connector_status_connected)
2590 intel_hdmi_set_edid(&connector->base);
2597 /* drm_edid_connector_update() done in ->detect() or ->force() */
2598 return drm_edid_connector_add_modes(&connector->base);
2607 ret = intel_connector_register(&connector->base);
2617 struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier;
2621 intel_connector_unregister(&connector->base);
2644 return intel_digital_connector_atomic_check(&connector->base, state);
2646 return g4x_hdmi_connector_atomic_check(&connector->base, state);
2661 intel_attach_force_audio_property(&connector->base);
2662 intel_attach_broadcast_rgb_property(&connector->base);
2663 intel_attach_aspect_ratio_property(&connector->base);
2665 intel_attach_hdmi_colorspace_property(&connector->base);
2666 drm_connector_attach_content_type_property(&connector->base);
2669 drm_connector_attach_hdr_output_metadata_property(&connector->base);
2672 drm_connector_attach_max_bpc_property(&connector->base, 8, 12);
2701 &connector->base.display_info.hdmi.scdc.scrambling;
2703 if (!sink_scrambling->supported)
2706 drm_dbg_kms(display->drm,
2708 connector->base.base.id, connector->base.name,
2712 return drm_scdc_set_high_tmds_clock_ratio(&connector->base, high_tmds_clock_ratio) &&
2713 drm_scdc_set_scrambling(&connector->base, scrambling);
2718 enum port port = encoder->port;
2741 enum port port = encoder->port;
2761 enum port port = encoder->port;
2788 enum port port = encoder->port;
2795 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port));
2827 WARN_ON(encoder->port == PORT_C);
2831 * final two outputs use type-c pins, even though they're actually
2832 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2836 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2846 drm_WARN_ON(display->drm, encoder->port == PORT_A);
2850 * final two outputs use type-c pins, even though they're actually
2851 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2855 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2869 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C);
2872 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2878 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2883 enum port port = encoder->port;
2909 if (display->platform.alderlake_s)
2913 else if (display->platform.rocketlake)
2917 else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
2924 else if (display->platform.geminilake || display->platform.broxton)
2926 else if (display->platform.cherryview)
2940 for_each_intel_encoder(display->drm, other) {
2949 connector = enc_to_dig_port(other)->hdmi.attached_connector;
2951 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
2965 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2974 drm_dbg_kms(display->drm,
2976 encoder->base.base.id, encoder->base.name, ddc_pin);
2982 drm_dbg_kms(display->drm,
2984 encoder->base.base.id, encoder->base.name, ddc_pin,
2985 other->base.base.id, other->base.name);
2989 drm_dbg_kms(display->drm,
2991 encoder->base.base.id, encoder->base.name,
3001 if (display->platform.valleyview || display->platform.cherryview) {
3002 dig_port->write_infoframe = vlv_write_infoframe;
3003 dig_port->read_infoframe = vlv_read_infoframe;
3004 dig_port->set_infoframes = vlv_set_infoframes;
3005 dig_port->infoframes_enabled = vlv_infoframes_enabled;
3006 } else if (display->platform.g4x) {
3007 dig_port->write_infoframe = g4x_write_infoframe;
3008 dig_port->read_infoframe = g4x_read_infoframe;
3009 dig_port->set_infoframes = g4x_set_infoframes;
3010 dig_port->infoframes_enabled = g4x_infoframes_enabled;
3012 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) {
3013 dig_port->write_infoframe = lspcon_write_infoframe;
3014 dig_port->read_infoframe = lspcon_read_infoframe;
3015 dig_port->set_infoframes = lspcon_set_infoframes;
3016 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3018 dig_port->write_infoframe = hsw_write_infoframe;
3019 dig_port->read_infoframe = hsw_read_infoframe;
3020 dig_port->set_infoframes = hsw_set_infoframes;
3021 dig_port->infoframes_enabled = hsw_infoframes_enabled;
3024 dig_port->write_infoframe = ibx_write_infoframe;
3025 dig_port->read_infoframe = ibx_read_infoframe;
3026 dig_port->set_infoframes = ibx_set_infoframes;
3027 dig_port->infoframes_enabled = ibx_infoframes_enabled;
3029 dig_port->write_infoframe = cpt_write_infoframe;
3030 dig_port->read_infoframe = cpt_read_infoframe;
3031 dig_port->set_infoframes = cpt_set_infoframes;
3032 dig_port->infoframes_enabled = cpt_infoframes_enabled;
3040 struct drm_connector *connector = &intel_connector->base;
3041 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3042 struct intel_encoder *intel_encoder = &dig_port->base;
3043 struct drm_device *dev = intel_encoder->base.dev;
3044 enum port port = intel_encoder->port;
3048 drm_dbg_kms(display->drm,
3050 intel_encoder->base.base.id, intel_encoder->base.name);
3055 if (drm_WARN(dev, dig_port->max_lanes < 4,
3057 dig_port->max_lanes, intel_encoder->base.base.id,
3058 intel_encoder->base.name))
3073 connector->interlace_allowed = true;
3075 connector->stereo_allowed = true;
3078 connector->ycbcr_420_allowed = true;
3080 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3081 intel_connector->base.polled = intel_connector->polled;
3084 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3086 intel_connector->get_hw_state = intel_connector_get_hw_state;
3091 intel_hdmi->attached_connector = intel_connector;
3097 drm_dbg_kms(display->drm,
3103 intel_hdmi->cec_notifier =
3104 cec_notifier_conn_register(dev->dev, port_identifier(port),
3106 if (!intel_hdmi->cec_notifier)
3107 drm_dbg_kms(display->drm, "CEC notifier get failed\n");
3113 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3137 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3172 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3183 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3184 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3207 * clock per slice (in MHz) as read from HF-VSDB.
3239 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3248 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3326 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3337 bpp_target_x16 -= bpp_decrement_x16;