Lines Matching defs:encoder
209 static void g4x_write_infoframe(struct intel_encoder *encoder,
214 struct intel_display *display = to_intel_display(encoder);
245 static void g4x_read_infoframe(struct intel_encoder *encoder,
250 struct intel_display *display = to_intel_display(encoder);
261 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
264 struct intel_display *display = to_intel_display(encoder);
270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
277 static void ibx_write_infoframe(struct intel_encoder *encoder,
282 struct intel_display *display = to_intel_display(encoder);
316 static void ibx_read_infoframe(struct intel_encoder *encoder,
321 struct intel_display *display = to_intel_display(encoder);
333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
336 struct intel_display *display = to_intel_display(encoder);
344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
352 static void cpt_write_infoframe(struct intel_encoder *encoder,
357 struct intel_display *display = to_intel_display(encoder);
394 static void cpt_read_infoframe(struct intel_encoder *encoder,
399 struct intel_display *display = to_intel_display(encoder);
411 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
414 struct intel_display *display = to_intel_display(encoder);
426 static void vlv_write_infoframe(struct intel_encoder *encoder,
431 struct intel_display *display = to_intel_display(encoder);
466 static void vlv_read_infoframe(struct intel_encoder *encoder,
471 struct intel_display *display = to_intel_display(encoder);
484 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
487 struct intel_display *display = to_intel_display(encoder);
494 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
502 void hsw_write_infoframe(struct intel_encoder *encoder,
507 struct intel_display *display = to_intel_display(encoder);
546 void hsw_read_infoframe(struct intel_encoder *encoder,
550 struct intel_display *display = to_intel_display(encoder);
560 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
563 struct intel_display *display = to_intel_display(encoder);
604 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
607 struct intel_display *display = to_intel_display(encoder);
608 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
612 val = dig_port->infoframes_enabled(encoder, crtc_state);
647 static void intel_write_infoframe(struct intel_encoder *encoder,
652 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
660 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
665 if (drm_WARN_ON(encoder->base.dev, len < 0))
673 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
676 void intel_read_infoframe(struct intel_encoder *encoder,
681 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
689 dig_port->read_infoframe(encoder, crtc_state,
698 drm_dbg_kms(encoder->base.dev,
704 drm_dbg_kms(encoder->base.dev,
710 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
741 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
760 if (drm_WARN_ON(encoder->base.dev, ret))
767 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
771 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
786 if (drm_WARN_ON(encoder->base.dev, ret))
792 if (drm_WARN_ON(encoder->base.dev, ret))
799 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
818 if (drm_WARN_ON(encoder->base.dev, ret))
822 if (drm_WARN_ON(encoder->base.dev, ret))
829 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
833 struct intel_display *display = to_intel_display(encoder);
863 static void g4x_set_infoframes(struct intel_encoder *encoder,
868 struct intel_display *display = to_intel_display(encoder);
869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
873 u32 port = VIDEO_DIP_PORT(encoder->port);
922 intel_write_infoframe(encoder, crtc_state,
925 intel_write_infoframe(encoder, crtc_state,
928 intel_write_infoframe(encoder, crtc_state,
976 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
980 struct intel_display *display = to_intel_display(encoder);
981 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1006 struct intel_display *display = to_intel_display(encoder);
1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1027 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1049 static void ibx_set_infoframes(struct intel_encoder *encoder,
1054 struct intel_display *display = to_intel_display(encoder);
1056 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1060 u32 port = VIDEO_DIP_PORT(encoder->port);
1091 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1097 intel_write_infoframe(encoder, crtc_state,
1100 intel_write_infoframe(encoder, crtc_state,
1103 intel_write_infoframe(encoder, crtc_state,
1108 static void cpt_set_infoframes(struct intel_encoder *encoder,
1113 struct intel_display *display = to_intel_display(encoder);
1115 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1140 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1146 intel_write_infoframe(encoder, crtc_state,
1149 intel_write_infoframe(encoder, crtc_state,
1152 intel_write_infoframe(encoder, crtc_state,
1157 static void vlv_set_infoframes(struct intel_encoder *encoder,
1162 struct intel_display *display = to_intel_display(encoder);
1164 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1167 u32 port = VIDEO_DIP_PORT(encoder->port);
1198 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1204 intel_write_infoframe(encoder, crtc_state,
1207 intel_write_infoframe(encoder, crtc_state,
1210 intel_write_infoframe(encoder, crtc_state,
1215 void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
1219 struct intel_display *display = to_intel_display(encoder);
1234 intel_write_infoframe(encoder, crtc_state,
1239 static void hsw_set_infoframes(struct intel_encoder *encoder,
1244 struct intel_display *display = to_intel_display(encoder);
1263 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1269 intel_write_infoframe(encoder, crtc_state,
1272 intel_write_infoframe(encoder, crtc_state,
1275 intel_write_infoframe(encoder, crtc_state,
1278 intel_write_infoframe(encoder, crtc_state,
1813 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1815 struct intel_display *display = to_intel_display(encoder);
1816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1830 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1855 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1856 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1883 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1905 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200)
1909 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)
2112 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2116 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2147 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2151 struct intel_display *display = to_intel_display(encoder);
2159 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2209 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2246 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2251 struct intel_display *display = to_intel_display(encoder);
2268 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2278 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2290 static bool source_supports_scrambling(struct intel_encoder *encoder)
2306 return intel_hdmi_source_max_tmds_clock(encoder) > 340000;
2309 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
2313 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
2319 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2323 struct intel_display *display = to_intel_display(encoder);
2345 intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2346 intel_audio_compute_config(encoder, pipe_config, conn_state);
2352 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2354 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2377 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2387 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2390 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2395 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2400 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2405 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2413 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2415 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2442 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2459 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2482 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2536 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2551 !intel_digital_port_connected(encoder))
2665 * @encoder: intel_encoder
2681 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2686 struct intel_display *display = to_intel_display(encoder);
2703 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder)
2705 enum port port = encoder->port;
2726 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder)
2728 enum port port = encoder->port;
2746 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder)
2748 enum port port = encoder->port;
2772 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder)
2774 struct intel_display *display = to_intel_display(encoder);
2775 enum port port = encoder->port;
2777 if (intel_encoder_is_combo(encoder))
2779 else if (intel_encoder_is_tc(encoder))
2780 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder);
2786 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder)
2788 enum phy phy = intel_encoder_to_phy(encoder);
2809 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder)
2811 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2812 enum phy phy = intel_encoder_to_phy(encoder);
2814 WARN_ON(encoder->port == PORT_C);
2828 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder)
2830 struct intel_display *display = to_intel_display(encoder);
2831 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2832 enum phy phy = intel_encoder_to_phy(encoder);
2834 drm_WARN_ON(display->drm, encoder->port == PORT_A);
2848 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder)
2850 return intel_encoder_to_phy(encoder) + 1;
2853 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder)
2855 enum phy phy = intel_encoder_to_phy(encoder);
2857 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C);
2869 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder)
2871 enum port port = encoder->port;
2892 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)
2894 struct intel_display *display = to_intel_display(encoder);
2895 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2899 ddc_pin = adls_encoder_to_ddc_pin(encoder);
2901 ddc_pin = dg1_encoder_to_ddc_pin(encoder);
2903 ddc_pin = rkl_encoder_to_ddc_pin(encoder);
2905 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder);
2908 ddc_pin = mcc_encoder_to_ddc_pin(encoder);
2910 ddc_pin = icl_encoder_to_ddc_pin(encoder);
2912 ddc_pin = cnp_encoder_to_ddc_pin(encoder);
2914 ddc_pin = bxt_encoder_to_ddc_pin(encoder);
2916 ddc_pin = chv_encoder_to_ddc_pin(encoder);
2918 ddc_pin = g4x_encoder_to_ddc_pin(encoder);
2924 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
2926 struct intel_display *display = to_intel_display(encoder);
2932 if (other == encoder)
2947 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2949 struct intel_display *display = to_intel_display(encoder);
2954 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2958 ddc_pin = intel_hdmi_default_ddc_pin(encoder);
2965 encoder->base.base.id, encoder->base.name, ddc_pin);
2969 other = get_encoder_by_ddc_pin(encoder, ddc_pin);
2973 encoder->base.base.id, encoder->base.name, ddc_pin,
2980 encoder->base.base.id, encoder->base.name,
3128 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3132 * @src_max_slices: maximum slices supported by the DSC encoder
3133 * @src_max_slice_width: maximum slice width supported by DSC encoder
3137 * @return: num of dsc slices that can be supported by the dsc encoder
3210 * of PCON encoder and HDMI decoder can support.
3266 * fractional bpp, if supported by PCON DSC encoder
3304 * encoder. For fractional BPP we use bpp_target as a multiple of 16.