Lines Matching +full:display +full:- +full:hint
28 * compressing the amount of memory used by the display. It is total
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
67 for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id))
71 for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
94 struct intel_display *display; member
123 * and re-enable FBC for a new configuration we just check if there's
134 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_fbc_plane_stride()
137 stride = plane_state->view.color_plane[0].mapping_stride; in intel_fbc_plane_stride()
138 if (!drm_rotation_90_or_270(plane_state->hw.rotation)) in intel_fbc_plane_stride()
139 stride /= fb->format->cpp[0]; in intel_fbc_plane_stride()
158 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
172 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
186 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
195 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
196 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
203 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride() local
205 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; in intel_fbc_cfb_stride()
208 return _intel_fbc_cfb_stride(display, cpp, width, stride); in intel_fbc_cfb_stride()
216 static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) in intel_fbc_max_cfb_height() argument
218 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_cfb_height()
220 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
222 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in intel_fbc_max_cfb_height()
228 static unsigned int _intel_fbc_cfb_size(struct intel_display *display, in _intel_fbc_cfb_size() argument
231 return min(height, intel_fbc_max_cfb_height(display)) * stride; in _intel_fbc_cfb_size()
236 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_size() local
237 unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16; in intel_fbc_cfb_size()
239 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); in intel_fbc_cfb_size()
244 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_override_cfb_stride() local
247 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_fbc_override_cfb_stride()
257 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) in intel_fbc_override_cfb_stride()
263 static bool intel_fbc_has_fences(struct intel_display *display) in intel_fbc_has_fences() argument
265 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); in intel_fbc_has_fences()
272 const struct intel_fbc_state *fbc_state = &fbc->state; in i8xx_fbc_ctl()
273 struct intel_display *display = fbc->display; in i8xx_fbc_ctl() local
274 struct drm_i915_private *i915 = to_i915(display->drm); in i8xx_fbc_ctl()
278 cfb_stride = fbc_state->cfb_stride / fbc->limit; in i8xx_fbc_ctl()
281 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
282 cfb_stride = (cfb_stride / 32) - 1; in i8xx_fbc_ctl()
284 cfb_stride = (cfb_stride / 64) - 1; in i8xx_fbc_ctl()
287 FBC_CTL_INTERVAL(fbc_state->interval) | in i8xx_fbc_ctl()
293 if (fbc_state->fence_id >= 0) in i8xx_fbc_ctl()
294 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id); in i8xx_fbc_ctl()
301 const struct intel_fbc_state *fbc_state = &fbc->state; in i965_fbc_ctl2()
305 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane); in i965_fbc_ctl2()
307 if (fbc_state->fence_id >= 0) in i965_fbc_ctl2()
315 struct intel_display *display = fbc->display; in i8xx_fbc_deactivate() local
319 fbc_ctl = intel_de_read(display, FBC_CONTROL); in i8xx_fbc_deactivate()
324 intel_de_write(display, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
327 if (intel_de_wait_for_clear(display, FBC_STATUS, in i8xx_fbc_deactivate()
329 drm_dbg_kms(display->drm, "FBC idle timed out\n"); in i8xx_fbc_deactivate()
336 const struct intel_fbc_state *fbc_state = &fbc->state; in i8xx_fbc_activate()
337 struct intel_display *display = fbc->display; in i8xx_fbc_activate() local
342 intel_de_write(display, FBC_TAG(i), 0); in i8xx_fbc_activate()
344 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
345 intel_de_write(display, FBC_CONTROL2, in i8xx_fbc_activate()
347 intel_de_write(display, FBC_FENCE_OFF, in i8xx_fbc_activate()
348 fbc_state->fence_y_offset); in i8xx_fbc_activate()
351 intel_de_write(display, FBC_CONTROL, in i8xx_fbc_activate()
357 return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_is_active()
362 return intel_de_read(fbc->display, FBC_STATUS) & in i8xx_fbc_is_compressing()
368 struct intel_fbc_state *fbc_state = &fbc->state; in i8xx_fbc_nuke()
369 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; in i8xx_fbc_nuke()
370 struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); in i8xx_fbc_nuke()
378 struct intel_display *display = fbc->display; in i8xx_fbc_program_cfb() local
379 struct drm_i915_private *i915 = to_i915(display->drm); in i8xx_fbc_program_cfb()
381 drm_WARN_ON(display->drm, in i8xx_fbc_program_cfb()
383 i915_gem_stolen_node_offset(&fbc->compressed_fb), in i8xx_fbc_program_cfb()
385 drm_WARN_ON(display->drm, in i8xx_fbc_program_cfb()
387 i915_gem_stolen_node_offset(&fbc->compressed_llb), in i8xx_fbc_program_cfb()
390 i915_gem_stolen_node_address(i915, &fbc->compressed_fb)); in i8xx_fbc_program_cfb()
392 i915_gem_stolen_node_address(i915, &fbc->compressed_llb)); in i8xx_fbc_program_cfb()
406 struct intel_fbc_state *fbc_state = &fbc->state; in i965_fbc_nuke()
407 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; in i965_fbc_nuke()
408 struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); in i965_fbc_nuke()
425 switch (fbc->limit) { in g4x_dpfc_ctl_limit()
427 MISSING_CASE(fbc->limit); in g4x_dpfc_ctl_limit()
440 const struct intel_fbc_state *fbc_state = &fbc->state; in g4x_dpfc_ctl()
441 struct intel_display *display = fbc->display; in g4x_dpfc_ctl() local
442 struct drm_i915_private *i915 = to_i915(display->drm); in g4x_dpfc_ctl()
446 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane); in g4x_dpfc_ctl()
451 if (fbc_state->fence_id >= 0) { in g4x_dpfc_ctl()
454 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
455 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id); in g4x_dpfc_ctl()
463 const struct intel_fbc_state *fbc_state = &fbc->state; in g4x_fbc_activate()
464 struct intel_display *display = fbc->display; in g4x_fbc_activate() local
466 intel_de_write(display, DPFC_FENCE_YOFF, in g4x_fbc_activate()
467 fbc_state->fence_y_offset); in g4x_fbc_activate()
469 intel_de_write(display, DPFC_CONTROL, in g4x_fbc_activate()
475 struct intel_display *display = fbc->display; in g4x_fbc_deactivate() local
479 dpfc_ctl = intel_de_read(display, DPFC_CONTROL); in g4x_fbc_deactivate()
482 intel_de_write(display, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
488 return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_is_active()
493 return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK; in g4x_fbc_is_compressing()
498 struct intel_display *display = fbc->display; in g4x_fbc_program_cfb() local
500 intel_de_write(display, DPFC_CB_BASE, in g4x_fbc_program_cfb()
501 i915_gem_stolen_node_offset(&fbc->compressed_fb)); in g4x_fbc_program_cfb()
515 struct intel_fbc_state *fbc_state = &fbc->state; in ilk_fbc_activate()
516 struct intel_display *display = fbc->display; in ilk_fbc_activate() local
518 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), in ilk_fbc_activate()
519 fbc_state->fence_y_offset); in ilk_fbc_activate()
521 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), in ilk_fbc_activate()
527 struct intel_display *display = fbc->display; in ilk_fbc_deactivate() local
531 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); in ilk_fbc_deactivate()
534 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); in ilk_fbc_deactivate()
540 return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; in ilk_fbc_is_active()
545 return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; in ilk_fbc_is_compressing()
550 struct intel_display *display = fbc->display; in ilk_fbc_program_cfb() local
552 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), in ilk_fbc_program_cfb()
553 i915_gem_stolen_node_offset(&fbc->compressed_fb)); in ilk_fbc_program_cfb()
567 const struct intel_fbc_state *fbc_state = &fbc->state; in snb_fbc_program_fence()
568 struct intel_display *display = fbc->display; in snb_fbc_program_fence() local
571 if (fbc_state->fence_id >= 0) in snb_fbc_program_fence()
572 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id); in snb_fbc_program_fence()
574 intel_de_write(display, SNB_DPFC_CTL_SA, ctl); in snb_fbc_program_fence()
575 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); in snb_fbc_program_fence()
587 struct intel_display *display = fbc->display; in snb_fbc_nuke() local
589 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); in snb_fbc_nuke()
590 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id)); in snb_fbc_nuke()
604 const struct intel_fbc_state *fbc_state = &fbc->state; in glk_fbc_program_cfb_stride()
605 struct intel_display *display = fbc->display; in glk_fbc_program_cfb_stride() local
608 if (fbc_state->override_cfb_stride) in glk_fbc_program_cfb_stride()
610 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); in glk_fbc_program_cfb_stride()
612 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val); in glk_fbc_program_cfb_stride()
617 const struct intel_fbc_state *fbc_state = &fbc->state; in skl_fbc_program_cfb_stride()
618 struct intel_display *display = fbc->display; in skl_fbc_program_cfb_stride() local
621 /* Display WA #0529: skl, kbl, bxt. */ in skl_fbc_program_cfb_stride()
622 if (fbc_state->override_cfb_stride) in skl_fbc_program_cfb_stride()
624 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); in skl_fbc_program_cfb_stride()
626 intel_de_rmw(display, CHICKEN_MISC_4, in skl_fbc_program_cfb_stride()
633 const struct intel_fbc_state *fbc_state = &fbc->state; in ivb_dpfc_ctl()
634 struct intel_display *display = fbc->display; in ivb_dpfc_ctl() local
635 struct drm_i915_private *i915 = to_i915(display->drm); in ivb_dpfc_ctl()
641 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); in ivb_dpfc_ctl()
643 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
644 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); in ivb_dpfc_ctl()
646 if (fbc_state->fence_id >= 0) in ivb_dpfc_ctl()
649 if (fbc->false_color) in ivb_dpfc_ctl()
657 struct intel_display *display = fbc->display; in ivb_fbc_activate() local
660 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
662 else if (DISPLAY_VER(display) == 9) in ivb_fbc_activate()
665 if (intel_fbc_has_fences(display)) in ivb_fbc_activate()
670 if (DISPLAY_VER(display) >= 20) in ivb_fbc_activate()
671 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); in ivb_fbc_activate()
673 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_activate()
679 return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; in ivb_fbc_is_compressing()
685 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_set_false_color()
701 return fbc->funcs->is_active(fbc); in intel_fbc_hw_is_active()
706 trace_intel_fbc_activate(fbc->state.plane); in intel_fbc_hw_activate()
708 fbc->active = true; in intel_fbc_hw_activate()
709 fbc->activated = true; in intel_fbc_hw_activate()
711 fbc->funcs->activate(fbc); in intel_fbc_hw_activate()
716 trace_intel_fbc_deactivate(fbc->state.plane); in intel_fbc_hw_deactivate()
718 fbc->active = false; in intel_fbc_hw_deactivate()
720 fbc->funcs->deactivate(fbc); in intel_fbc_hw_deactivate()
725 return fbc->funcs->is_compressing(fbc); in intel_fbc_is_compressing()
730 struct intel_display *display = fbc->display; in intel_fbc_nuke() local
732 lockdep_assert_held(&fbc->lock); in intel_fbc_nuke()
733 drm_WARN_ON(display->drm, fbc->flip_pending); in intel_fbc_nuke()
735 trace_intel_fbc_nuke(fbc->state.plane); in intel_fbc_nuke()
737 fbc->funcs->nuke(fbc); in intel_fbc_nuke()
742 lockdep_assert_held(&fbc->lock); in intel_fbc_activate()
747 fbc->no_fbc_reason = NULL; in intel_fbc_activate()
752 lockdep_assert_held(&fbc->lock); in intel_fbc_deactivate()
754 if (fbc->active) in intel_fbc_deactivate()
757 fbc->no_fbc_reason = reason; in intel_fbc_deactivate()
760 static u64 intel_fbc_cfb_base_max(struct intel_display *display) in intel_fbc_cfb_base_max() argument
762 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_cfb_base_max()
764 if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in intel_fbc_cfb_base_max()
770 static u64 intel_fbc_stolen_end(struct intel_display *display) in intel_fbc_stolen_end() argument
772 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); in intel_fbc_stolen_end()
780 (DISPLAY_VER(display) == 9 && !IS_BROXTON(i915))) in intel_fbc_stolen_end()
781 end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024; in intel_fbc_stolen_end()
785 return min(end, intel_fbc_cfb_base_max(display)); in intel_fbc_stolen_end()
790 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1; in intel_fbc_min_limit()
793 static int intel_fbc_max_limit(struct intel_display *display) in intel_fbc_max_limit() argument
795 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_limit()
811 struct intel_display *display = fbc->display; in find_compression_limit() local
812 struct drm_i915_private *i915 = to_i915(display->drm); in find_compression_limit()
813 u64 end = intel_fbc_stolen_end(display); in find_compression_limit()
818 /* Try to over-allocate to reduce reallocations and fragmentation. */ in find_compression_limit()
819 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, in find_compression_limit()
824 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { in find_compression_limit()
825 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb, in find_compression_limit()
837 struct intel_display *display = fbc->display; in intel_fbc_alloc_cfb() local
838 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_alloc_cfb()
841 drm_WARN_ON(display->drm, in intel_fbc_alloc_cfb()
842 i915_gem_stolen_node_allocated(&fbc->compressed_fb)); in intel_fbc_alloc_cfb()
843 drm_WARN_ON(display->drm, in intel_fbc_alloc_cfb()
844 i915_gem_stolen_node_allocated(&fbc->compressed_llb)); in intel_fbc_alloc_cfb()
846 if (DISPLAY_VER(display) < 5 && !IS_G4X(i915)) { in intel_fbc_alloc_cfb()
847 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb, in intel_fbc_alloc_cfb()
857 drm_info_once(display->drm, in intel_fbc_alloc_cfb()
858 …pressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to incr… in intel_fbc_alloc_cfb()
860 fbc->limit = ret; in intel_fbc_alloc_cfb()
862 drm_dbg_kms(display->drm, in intel_fbc_alloc_cfb()
864 i915_gem_stolen_node_size(&fbc->compressed_fb), fbc->limit); in intel_fbc_alloc_cfb()
868 if (i915_gem_stolen_node_allocated(&fbc->compressed_llb)) in intel_fbc_alloc_cfb()
869 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); in intel_fbc_alloc_cfb()
872 drm_info_once(display->drm, in intel_fbc_alloc_cfb()
873 …"not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be a… in intel_fbc_alloc_cfb()
874 return -ENOSPC; in intel_fbc_alloc_cfb()
879 fbc->funcs->program_cfb(fbc); in intel_fbc_program_cfb()
884 struct intel_display *display = fbc->display; in intel_fbc_program_workarounds() local
885 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_program_workarounds()
890 * Display WA #0883: skl,bxt in intel_fbc_program_workarounds()
892 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
900 * Display WA #0873: skl,kbl,cfl in intel_fbc_program_workarounds()
902 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
907 if (IS_DISPLAY_VER(display, 11, 12)) in intel_fbc_program_workarounds()
908 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
912 if (DISPLAY_VER(display) >= 11 && !IS_DG2(i915)) in intel_fbc_program_workarounds()
913 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
919 struct intel_display *display = fbc->display; in __intel_fbc_cleanup_cfb() local
920 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_fbc_cleanup_cfb()
925 if (i915_gem_stolen_node_allocated(&fbc->compressed_llb)) in __intel_fbc_cleanup_cfb()
926 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb); in __intel_fbc_cleanup_cfb()
927 if (i915_gem_stolen_node_allocated(&fbc->compressed_fb)) in __intel_fbc_cleanup_cfb()
928 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb); in __intel_fbc_cleanup_cfb()
931 void intel_fbc_cleanup(struct intel_display *display) in intel_fbc_cleanup() argument
936 for_each_intel_fbc(display, fbc, fbc_id) { in intel_fbc_cleanup()
937 mutex_lock(&fbc->lock); in intel_fbc_cleanup()
939 mutex_unlock(&fbc->lock); in intel_fbc_cleanup()
947 const struct drm_framebuffer *fb = plane_state->hw.fb; in i8xx_fbc_stride_is_valid()
949 fb->format->cpp[0]; in i8xx_fbc_stride_is_valid()
956 const struct drm_framebuffer *fb = plane_state->hw.fb; in i965_fbc_stride_is_valid()
958 fb->format->cpp[0]; in i965_fbc_stride_is_valid()
970 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_fbc_stride_is_valid()
972 fb->format->cpp[0]; in skl_fbc_stride_is_valid()
974 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ in skl_fbc_stride_is_valid()
975 if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) in skl_fbc_stride_is_valid()
988 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in stride_is_valid() local
989 struct drm_i915_private *i915 = to_i915(display->drm); in stride_is_valid()
991 if (DISPLAY_VER(display) >= 11) in stride_is_valid()
993 else if (DISPLAY_VER(display) >= 9) in stride_is_valid()
995 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in stride_is_valid()
997 else if (DISPLAY_VER(display) == 4) in stride_is_valid()
1005 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in i8xx_fbc_pixel_format_is_valid() local
1006 const struct drm_framebuffer *fb = plane_state->hw.fb; in i8xx_fbc_pixel_format_is_valid()
1008 switch (fb->format->format) { in i8xx_fbc_pixel_format_is_valid()
1015 if (DISPLAY_VER(display) == 2) in i8xx_fbc_pixel_format_is_valid()
1025 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in g4x_fbc_pixel_format_is_valid() local
1026 struct drm_i915_private *i915 = to_i915(display->drm); in g4x_fbc_pixel_format_is_valid()
1027 const struct drm_framebuffer *fb = plane_state->hw.fb; in g4x_fbc_pixel_format_is_valid()
1029 switch (fb->format->format) { in g4x_fbc_pixel_format_is_valid()
1045 const struct drm_framebuffer *fb = plane_state->hw.fb; in lnl_fbc_pixel_format_is_valid()
1047 switch (fb->format->format) { in lnl_fbc_pixel_format_is_valid()
1061 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in pixel_format_is_valid() local
1062 struct drm_i915_private *i915 = to_i915(display->drm); in pixel_format_is_valid()
1064 if (DISPLAY_VER(display) >= 20) in pixel_format_is_valid()
1066 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in pixel_format_is_valid()
1074 return plane_state->hw.rotation == DRM_MODE_ROTATE_0; in i8xx_fbc_rotation_is_valid()
1084 const struct drm_framebuffer *fb = plane_state->hw.fb; in skl_fbc_rotation_is_valid()
1085 unsigned int rotation = plane_state->hw.rotation; in skl_fbc_rotation_is_valid()
1087 if (fb->format->format == DRM_FORMAT_RGB565 && in skl_fbc_rotation_is_valid()
1096 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in rotation_is_valid() local
1097 struct drm_i915_private *i915 = to_i915(display->drm); in rotation_is_valid()
1099 if (DISPLAY_VER(display) >= 9) in rotation_is_valid()
1101 else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) in rotation_is_valid()
1107 static void intel_fbc_max_surface_size(struct intel_display *display, in intel_fbc_max_surface_size() argument
1110 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_surface_size()
1112 if (DISPLAY_VER(display) >= 11) { in intel_fbc_max_surface_size()
1115 } else if (DISPLAY_VER(display) >= 10) { in intel_fbc_max_surface_size()
1118 } else if (DISPLAY_VER(display) >= 7) { in intel_fbc_max_surface_size()
1121 } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { in intel_fbc_max_surface_size()
1132 * programmed as the display plane base address register. It does not look at
1138 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_surface_size_ok() local
1141 intel_fbc_max_surface_size(display, &max_w, &max_h); in intel_fbc_surface_size_ok()
1143 effective_w = plane_state->view.color_plane[0].x + in intel_fbc_surface_size_ok()
1144 (drm_rect_width(&plane_state->uapi.src) >> 16); in intel_fbc_surface_size_ok()
1145 effective_h = plane_state->view.color_plane[0].y + in intel_fbc_surface_size_ok()
1146 (drm_rect_height(&plane_state->uapi.src) >> 16); in intel_fbc_surface_size_ok()
1151 static void intel_fbc_max_plane_size(struct intel_display *display, in intel_fbc_max_plane_size() argument
1154 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_max_plane_size()
1156 if (DISPLAY_VER(display) >= 10) { in intel_fbc_max_plane_size()
1159 } else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(i915)) { in intel_fbc_max_plane_size()
1162 } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { in intel_fbc_max_plane_size()
1173 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_plane_size_valid() local
1176 intel_fbc_max_plane_size(display, &max_w, &max_h); in intel_fbc_plane_size_valid()
1178 w = drm_rect_width(&plane_state->uapi.src) >> 16; in intel_fbc_plane_size_valid()
1179 h = drm_rect_height(&plane_state->uapi.src) >> 16; in intel_fbc_plane_size_valid()
1186 const struct drm_framebuffer *fb = plane_state->hw.fb; in i8xx_fbc_tiling_valid()
1188 return fb->modifier == I915_FORMAT_MOD_X_TILED; in i8xx_fbc_tiling_valid()
1198 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in tiling_is_valid() local
1200 if (DISPLAY_VER(display) >= 9) in tiling_is_valid()
1210 struct intel_display *display = to_intel_display(state->base.dev); in intel_fbc_update_state() local
1215 struct intel_fbc *fbc = plane->fbc; in intel_fbc_update_state()
1216 struct intel_fbc_state *fbc_state = &fbc->state; in intel_fbc_update_state()
1218 WARN_ON(plane_state->no_fbc_reason); in intel_fbc_update_state()
1219 WARN_ON(fbc_state->plane && fbc_state->plane != plane); in intel_fbc_update_state()
1221 fbc_state->plane = plane; in intel_fbc_update_state()
1224 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); in intel_fbc_update_state()
1226 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); in intel_fbc_update_state()
1228 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && in intel_fbc_update_state()
1229 !intel_fbc_has_fences(display)); in intel_fbc_update_state()
1231 if (plane_state->flags & PLANE_HAS_FENCE) in intel_fbc_update_state()
1232 fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma); in intel_fbc_update_state()
1234 fbc_state->fence_id = -1; in intel_fbc_update_state()
1236 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); in intel_fbc_update_state()
1237 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); in intel_fbc_update_state()
1238 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); in intel_fbc_update_state()
1243 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_is_fence_ok() local
1257 return DISPLAY_VER(display) >= 9 || in intel_fbc_is_fence_ok()
1258 (plane_state->flags & PLANE_HAS_FENCE && in intel_fbc_is_fence_ok()
1259 i915_vma_fence_id(plane_state->ggtt_vma) != -1); in intel_fbc_is_fence_ok()
1264 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_fbc_is_cfb_ok()
1265 struct intel_fbc *fbc = plane->fbc; in intel_fbc_is_cfb_ok()
1267 return intel_fbc_min_limit(plane_state) <= fbc->limit && in intel_fbc_is_cfb_ok()
1268 intel_fbc_cfb_size(plane_state) <= fbc->limit * in intel_fbc_is_cfb_ok()
1269 i915_gem_stolen_node_size(&fbc->compressed_fb); in intel_fbc_is_cfb_ok()
1274 return !plane_state->no_fbc_reason && in intel_fbc_is_ok()
1282 struct intel_display *display = to_intel_display(state->base.dev); in intel_fbc_check_plane() local
1283 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_check_plane()
1286 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_fbc_check_plane()
1287 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); in intel_fbc_check_plane()
1289 struct intel_fbc *fbc = plane->fbc; in intel_fbc_check_plane()
1295 plane_state->no_fbc_reason = "stolen memory not initialised"; in intel_fbc_check_plane()
1300 plane_state->no_fbc_reason = "VGPU active"; in intel_fbc_check_plane()
1304 if (!display->params.enable_fbc) { in intel_fbc_check_plane()
1305 plane_state->no_fbc_reason = "disabled per module param or by default"; in intel_fbc_check_plane()
1309 if (!plane_state->uapi.visible) { in intel_fbc_check_plane()
1310 plane_state->no_fbc_reason = "plane not visible"; in intel_fbc_check_plane()
1315 plane_state->no_fbc_reason = "Wa_16023588340"; in intel_fbc_check_plane()
1321 plane_state->no_fbc_reason = "VT-d enabled"; in intel_fbc_check_plane()
1327 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in intel_fbc_check_plane()
1328 plane_state->no_fbc_reason = "interlaced mode not supported"; in intel_fbc_check_plane()
1332 if (crtc_state->double_wide) { in intel_fbc_check_plane()
1333 plane_state->no_fbc_reason = "double wide pipe not supported"; in intel_fbc_check_plane()
1338 * Display 12+ is not supporting FBC with PSR2. in intel_fbc_check_plane()
1342 if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && in intel_fbc_check_plane()
1343 !crtc_state->has_panel_replay) { in intel_fbc_check_plane()
1344 plane_state->no_fbc_reason = "PSR2 enabled"; in intel_fbc_check_plane()
1349 if ((IS_DISPLAY_VER(display, 12, 13) || in intel_fbc_check_plane()
1351 crtc_state->has_psr && !crtc_state->has_panel_replay) { in intel_fbc_check_plane()
1352 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; in intel_fbc_check_plane()
1357 plane_state->no_fbc_reason = "pixel format not supported"; in intel_fbc_check_plane()
1362 plane_state->no_fbc_reason = "tiling not supported"; in intel_fbc_check_plane()
1367 plane_state->no_fbc_reason = "rotation not supported"; in intel_fbc_check_plane()
1372 plane_state->no_fbc_reason = "stride not supported"; in intel_fbc_check_plane()
1376 if (DISPLAY_VER(display) < 20 && in intel_fbc_check_plane()
1377 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && in intel_fbc_check_plane()
1378 fb->format->has_alpha) { in intel_fbc_check_plane()
1379 plane_state->no_fbc_reason = "per-pixel alpha not supported"; in intel_fbc_check_plane()
1384 plane_state->no_fbc_reason = "plane size too big"; in intel_fbc_check_plane()
1389 plane_state->no_fbc_reason = "surface size too big"; in intel_fbc_check_plane()
1398 if (DISPLAY_VER(display) >= 9 && in intel_fbc_check_plane()
1399 plane_state->view.color_plane[0].y & 3) { in intel_fbc_check_plane()
1400 plane_state->no_fbc_reason = "plane start Y offset misaligned"; in intel_fbc_check_plane()
1405 if (DISPLAY_VER(display) >= 11 && in intel_fbc_check_plane()
1406 (plane_state->view.color_plane[0].y + in intel_fbc_check_plane()
1407 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { in intel_fbc_check_plane()
1408 plane_state->no_fbc_reason = "plane end Y offset misaligned"; in intel_fbc_check_plane()
1420 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
1421 plane_state->no_fbc_reason = "pixel rate too high"; in intel_fbc_check_plane()
1426 plane_state->no_fbc_reason = NULL; in intel_fbc_check_plane()
1442 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb; in intel_fbc_can_flip_nuke()
1443 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb; in intel_fbc_can_flip_nuke()
1452 if (old_fb->format->format != new_fb->format->format) in intel_fbc_can_flip_nuke()
1455 if (old_fb->modifier != new_fb->modifier) in intel_fbc_can_flip_nuke()
1481 struct intel_display *display = to_intel_display(state->base.dev); in __intel_fbc_pre_update() local
1482 struct intel_fbc *fbc = plane->fbc; in __intel_fbc_pre_update()
1485 lockdep_assert_held(&fbc->lock); in __intel_fbc_pre_update()
1487 fbc->flip_pending = true; in __intel_fbc_pre_update()
1495 * Display WA #1198: glk+ in __intel_fbc_pre_update()
1507 if (fbc->activated && DISPLAY_VER(display) >= 10) in __intel_fbc_pre_update()
1509 fbc->activated = false; in __intel_fbc_pre_update()
1523 struct intel_fbc *fbc = plane->fbc; in intel_fbc_pre_update()
1525 if (!fbc || plane->pipe != crtc->pipe) in intel_fbc_pre_update()
1528 mutex_lock(&fbc->lock); in intel_fbc_pre_update()
1530 if (fbc->state.plane == plane) in intel_fbc_pre_update()
1533 mutex_unlock(&fbc->lock); in intel_fbc_pre_update()
1541 struct intel_display *display = fbc->display; in __intel_fbc_disable() local
1542 struct intel_plane *plane = fbc->state.plane; in __intel_fbc_disable()
1544 lockdep_assert_held(&fbc->lock); in __intel_fbc_disable()
1545 drm_WARN_ON(display->drm, fbc->active); in __intel_fbc_disable()
1547 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", in __intel_fbc_disable()
1548 plane->base.base.id, plane->base.name); in __intel_fbc_disable()
1552 fbc->state.plane = NULL; in __intel_fbc_disable()
1553 fbc->flip_pending = false; in __intel_fbc_disable()
1554 fbc->busy_bits = 0; in __intel_fbc_disable()
1559 lockdep_assert_held(&fbc->lock); in __intel_fbc_post_update()
1561 fbc->flip_pending = false; in __intel_fbc_post_update()
1562 fbc->busy_bits = 0; in __intel_fbc_post_update()
1575 struct intel_fbc *fbc = plane->fbc; in intel_fbc_post_update()
1577 if (!fbc || plane->pipe != crtc->pipe) in intel_fbc_post_update()
1580 mutex_lock(&fbc->lock); in intel_fbc_post_update()
1582 if (fbc->state.plane == plane) in intel_fbc_post_update()
1585 mutex_unlock(&fbc->lock); in intel_fbc_post_update()
1591 if (fbc->state.plane) in intel_fbc_get_frontbuffer_bit()
1592 return fbc->state.plane->frontbuffer_bit; in intel_fbc_get_frontbuffer_bit()
1604 mutex_lock(&fbc->lock); in __intel_fbc_invalidate()
1610 fbc->busy_bits |= frontbuffer_bits; in __intel_fbc_invalidate()
1614 mutex_unlock(&fbc->lock); in __intel_fbc_invalidate()
1624 for_each_intel_fbc(&i915->display, fbc, fbc_id) in intel_fbc_invalidate()
1633 mutex_lock(&fbc->lock); in __intel_fbc_flush()
1639 fbc->busy_bits &= ~frontbuffer_bits; in __intel_fbc_flush()
1644 if (fbc->busy_bits || fbc->flip_pending) in __intel_fbc_flush()
1647 if (fbc->active) in __intel_fbc_flush()
1653 mutex_unlock(&fbc->lock); in __intel_fbc_flush()
1663 for_each_intel_fbc(&i915->display, fbc, fbc_id) in intel_fbc_flush()
1688 struct intel_display *display = to_intel_display(state->base.dev); in __intel_fbc_enable() local
1691 struct intel_fbc *fbc = plane->fbc; in __intel_fbc_enable()
1693 lockdep_assert_held(&fbc->lock); in __intel_fbc_enable()
1695 if (fbc->state.plane) { in __intel_fbc_enable()
1696 if (fbc->state.plane != plane) in __intel_fbc_enable()
1707 drm_WARN_ON(display->drm, fbc->active); in __intel_fbc_enable()
1709 fbc->no_fbc_reason = plane_state->no_fbc_reason; in __intel_fbc_enable()
1710 if (fbc->no_fbc_reason) in __intel_fbc_enable()
1714 fbc->no_fbc_reason = "framebuffer not fenced"; in __intel_fbc_enable()
1718 if (fbc->underrun_detected) { in __intel_fbc_enable()
1719 fbc->no_fbc_reason = "FIFO underrun"; in __intel_fbc_enable()
1725 fbc->no_fbc_reason = "not enough stolen memory"; in __intel_fbc_enable()
1729 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n", in __intel_fbc_enable()
1730 plane->base.base.id, plane->base.name); in __intel_fbc_enable()
1731 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; in __intel_fbc_enable()
1740 * intel_fbc_disable - disable FBC if it's associated with crtc
1747 struct intel_display *display = to_intel_display(crtc->base.dev); in intel_fbc_disable() local
1750 for_each_intel_plane(display->drm, plane) { in intel_fbc_disable()
1751 struct intel_fbc *fbc = plane->fbc; in intel_fbc_disable()
1753 if (!fbc || plane->pipe != crtc->pipe) in intel_fbc_disable()
1756 mutex_lock(&fbc->lock); in intel_fbc_disable()
1757 if (fbc->state.plane == plane) in intel_fbc_disable()
1759 mutex_unlock(&fbc->lock); in intel_fbc_disable()
1773 struct intel_fbc *fbc = plane->fbc; in intel_fbc_update()
1775 if (!fbc || plane->pipe != crtc->pipe) in intel_fbc_update()
1778 mutex_lock(&fbc->lock); in intel_fbc_update()
1781 plane_state->no_fbc_reason) { in intel_fbc_update()
1782 if (fbc->state.plane == plane) in intel_fbc_update()
1788 mutex_unlock(&fbc->lock); in intel_fbc_update()
1795 struct intel_display *display = fbc->display; in intel_fbc_underrun_work_fn() local
1797 mutex_lock(&fbc->lock); in intel_fbc_underrun_work_fn()
1800 if (fbc->underrun_detected || !fbc->state.plane) in intel_fbc_underrun_work_fn()
1803 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n"); in intel_fbc_underrun_work_fn()
1804 fbc->underrun_detected = true; in intel_fbc_underrun_work_fn()
1807 if (!fbc->flip_pending) in intel_fbc_underrun_work_fn()
1808 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe)); in intel_fbc_underrun_work_fn()
1811 mutex_unlock(&fbc->lock); in intel_fbc_underrun_work_fn()
1816 struct intel_display *display = fbc->display; in __intel_fbc_reset_underrun() local
1818 cancel_work_sync(&fbc->underrun_work); in __intel_fbc_reset_underrun()
1820 mutex_lock(&fbc->lock); in __intel_fbc_reset_underrun()
1822 if (fbc->underrun_detected) { in __intel_fbc_reset_underrun()
1823 drm_dbg_kms(display->drm, in __intel_fbc_reset_underrun()
1824 "Re-allowing FBC after fifo underrun\n"); in __intel_fbc_reset_underrun()
1825 fbc->no_fbc_reason = "FIFO underrun cleared"; in __intel_fbc_reset_underrun()
1828 fbc->underrun_detected = false; in __intel_fbc_reset_underrun()
1829 mutex_unlock(&fbc->lock); in __intel_fbc_reset_underrun()
1833 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1834 * @display: display
1837 * want to re-enable FBC after an underrun to increase test coverage.
1839 void intel_fbc_reset_underrun(struct intel_display *display) in intel_fbc_reset_underrun() argument
1844 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_reset_underrun()
1850 struct drm_i915_private *i915 = to_i915(fbc->display->drm); in __intel_fbc_handle_fifo_underrun_irq()
1860 if (READ_ONCE(fbc->underrun_detected)) in __intel_fbc_handle_fifo_underrun_irq()
1863 queue_work(i915->unordered_wq, &fbc->underrun_work); in __intel_fbc_handle_fifo_underrun_irq()
1867 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1868 * @display: display
1880 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) in intel_fbc_handle_fifo_underrun_irq() argument
1885 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_handle_fifo_underrun_irq()
1898 static int intel_sanitize_fbc_option(struct intel_display *display) in intel_sanitize_fbc_option() argument
1900 struct drm_i915_private *i915 = to_i915(display->drm); in intel_sanitize_fbc_option()
1902 if (display->params.enable_fbc >= 0) in intel_sanitize_fbc_option()
1903 return !!display->params.enable_fbc; in intel_sanitize_fbc_option()
1905 if (!HAS_FBC(display)) in intel_sanitize_fbc_option()
1908 if (IS_BROADWELL(i915) || DISPLAY_VER(display) >= 9) in intel_sanitize_fbc_option()
1916 plane->fbc = fbc; in intel_fbc_add_plane()
1919 static struct intel_fbc *intel_fbc_create(struct intel_display *display, in intel_fbc_create() argument
1922 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_create()
1929 fbc->id = fbc_id; in intel_fbc_create()
1930 fbc->display = display; in intel_fbc_create()
1931 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); in intel_fbc_create()
1932 mutex_init(&fbc->lock); in intel_fbc_create()
1934 if (DISPLAY_VER(display) >= 7) in intel_fbc_create()
1935 fbc->funcs = &ivb_fbc_funcs; in intel_fbc_create()
1936 else if (DISPLAY_VER(display) == 6) in intel_fbc_create()
1937 fbc->funcs = &snb_fbc_funcs; in intel_fbc_create()
1938 else if (DISPLAY_VER(display) == 5) in intel_fbc_create()
1939 fbc->funcs = &ilk_fbc_funcs; in intel_fbc_create()
1941 fbc->funcs = &g4x_fbc_funcs; in intel_fbc_create()
1942 else if (DISPLAY_VER(display) == 4) in intel_fbc_create()
1943 fbc->funcs = &i965_fbc_funcs; in intel_fbc_create()
1945 fbc->funcs = &i8xx_fbc_funcs; in intel_fbc_create()
1951 * intel_fbc_init - Initialize FBC
1952 * @display: display
1956 void intel_fbc_init(struct intel_display *display) in intel_fbc_init() argument
1960 display->params.enable_fbc = intel_sanitize_fbc_option(display); in intel_fbc_init()
1961 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n", in intel_fbc_init()
1962 display->params.enable_fbc); in intel_fbc_init()
1964 for_each_fbc_id(display, fbc_id) in intel_fbc_init()
1965 display->fbc[fbc_id] = intel_fbc_create(display, fbc_id); in intel_fbc_init()
1969 * intel_fbc_sanitize - Sanitize FBC
1970 * @display: display
1976 void intel_fbc_sanitize(struct intel_display *display) in intel_fbc_sanitize() argument
1981 for_each_intel_fbc(display, fbc, fbc_id) { in intel_fbc_sanitize()
1989 struct intel_fbc *fbc = m->private; in intel_fbc_debugfs_status_show()
1990 struct intel_display *display = fbc->display; in intel_fbc_debugfs_status_show() local
1991 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_debugfs_status_show()
1995 drm_modeset_lock_all(display->drm); in intel_fbc_debugfs_status_show()
1997 wakeref = intel_runtime_pm_get(&i915->runtime_pm); in intel_fbc_debugfs_status_show()
1998 mutex_lock(&fbc->lock); in intel_fbc_debugfs_status_show()
2000 if (fbc->active) { in intel_fbc_debugfs_status_show()
2005 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); in intel_fbc_debugfs_status_show()
2008 for_each_intel_plane(display->drm, plane) { in intel_fbc_debugfs_status_show()
2010 to_intel_plane_state(plane->base.state); in intel_fbc_debugfs_status_show()
2012 if (plane->fbc != fbc) in intel_fbc_debugfs_status_show()
2016 fbc->state.plane == plane ? '*' : ' ', in intel_fbc_debugfs_status_show()
2017 plane->base.base.id, plane->base.name, in intel_fbc_debugfs_status_show()
2018 plane_state->no_fbc_reason ?: "FBC possible"); in intel_fbc_debugfs_status_show()
2021 mutex_unlock(&fbc->lock); in intel_fbc_debugfs_status_show()
2022 intel_runtime_pm_put(&i915->runtime_pm, wakeref); in intel_fbc_debugfs_status_show()
2024 drm_modeset_unlock_all(display->drm); in intel_fbc_debugfs_status_show()
2035 *val = fbc->false_color; in intel_fbc_debugfs_false_color_get()
2044 mutex_lock(&fbc->lock); in intel_fbc_debugfs_false_color_set()
2046 fbc->false_color = val; in intel_fbc_debugfs_false_color_set()
2048 if (fbc->active) in intel_fbc_debugfs_false_color_set()
2049 fbc->funcs->set_false_color(fbc, fbc->false_color); in intel_fbc_debugfs_false_color_set()
2051 mutex_unlock(&fbc->lock); in intel_fbc_debugfs_false_color_set()
2067 if (fbc->funcs->set_false_color) in intel_fbc_debugfs_add()
2074 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in intel_fbc_crtc_debugfs_add()
2076 if (plane->fbc) in intel_fbc_crtc_debugfs_add()
2077 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry); in intel_fbc_crtc_debugfs_add()
2080 /* FIXME: remove this once igt is on board with per-crtc stuff */
2081 void intel_fbc_debugfs_register(struct intel_display *display) in intel_fbc_debugfs_register() argument
2083 struct drm_minor *minor = display->drm->primary; in intel_fbc_debugfs_register()
2086 fbc = display->fbc[INTEL_FBC_A]; in intel_fbc_debugfs_register()
2088 intel_fbc_debugfs_add(fbc, minor->debugfs_root); in intel_fbc_debugfs_register()