87 	struct intel_plane *plane;  member
135 /* plane stride in pixels */
153 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
207 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in intel_fbc_cfb_stride()
217  * additional lines (up to the actual plane height) will
238 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in intel_fbc_cfb_size()
246 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in intel_fbc_override_cfb_stride()
309 		FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);  in i965_fbc_ctl2()
374 	enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;  in i8xx_fbc_nuke()
412 	enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;  in i965_fbc_nuke()
449 		DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);  in g4x_dpfc_ctl()
660 		dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);  in ivb_dpfc_ctl()
663 		dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id);  in ivb_dpfc_ctl()
729 	trace_intel_fbc_activate(fbc->state.plane);  in intel_fbc_hw_activate()
739 	trace_intel_fbc_deactivate(fbc->state.plane);  in intel_fbc_hw_deactivate()
758 	trace_intel_fbc_nuke(fbc->state.plane);  in intel_fbc_nuke()
1021 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in stride_is_valid()
1037 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in i8xx_fbc_pixel_format_is_valid()
1057 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in g4x_fbc_pixel_format_is_valid()
1092 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in pixel_format_is_valid()
1126 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in rotation_is_valid()
1159  * programmed as the display plane base address register. It does not look at
1161  * instead of just looking at the plane size.
1165 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in intel_fbc_surface_size_ok()
1198 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in intel_fbc_plane_size_valid()
1223 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in tiling_is_valid()
1267 				  struct intel_plane *plane)  in intel_fbc_dirty_rect_update_noarm()  argument
1269 	struct intel_display *display = to_intel_display(plane);  in intel_fbc_dirty_rect_update_noarm()
1270 	struct intel_fbc *fbc = plane->fbc;  in intel_fbc_dirty_rect_update_noarm()
1277 	if (fbc->state.plane == plane)  in intel_fbc_dirty_rect_update_noarm()
1290 	 * Initializing the FBC HW with the whole plane area as the dirty rect.  in intel_fbc_hw_intialize_dirty_rect()
1301 				   struct intel_plane *plane)  in intel_fbc_update_state()  argument
1307 		intel_atomic_get_new_plane_state(state, plane);  in intel_fbc_update_state()
1308 	struct intel_fbc *fbc = plane->fbc;  in intel_fbc_update_state()
1312 	WARN_ON(fbc_state->plane && fbc_state->plane != plane);  in intel_fbc_update_state()
1314 	fbc_state->plane = plane;  in intel_fbc_update_state()
1336 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);  in intel_fbc_is_fence_ok()
1357 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_fbc_is_cfb_ok()  local
1358 	struct intel_fbc *fbc = plane->fbc;  in intel_fbc_is_cfb_ok()
1376 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in __intel_fbc_prepare_dirty_rect()  local
1377 	struct intel_fbc *fbc = plane->fbc;  in __intel_fbc_prepare_dirty_rect()
1406 	struct intel_plane *plane;  in intel_fbc_prepare_dirty_rect()  local
1412 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {  in intel_fbc_prepare_dirty_rect()
1413 		struct intel_fbc *fbc = plane->fbc;  in intel_fbc_prepare_dirty_rect()
1415 		if (!fbc || plane->pipe != crtc->pipe)  in intel_fbc_prepare_dirty_rect()
1420 		if (fbc->state.plane == plane)  in intel_fbc_prepare_dirty_rect()
1429 				 struct intel_plane *plane)  in intel_fbc_check_plane()  argument
1434 		intel_atomic_get_new_plane_state(state, plane);  in intel_fbc_check_plane()
1438 	struct intel_fbc *fbc = plane->fbc;  in intel_fbc_check_plane()
1459 		plane_state->no_fbc_reason = "plane not visible";  in intel_fbc_check_plane()
1539 		plane_state->no_fbc_reason = "plane size too big";  in intel_fbc_check_plane()
1549 	 * Work around a problem on GEN9+ HW, where enabling FBC on a plane  in intel_fbc_check_plane()
1555 		plane_state->no_fbc_reason = "plane start Y offset misaligned";  in intel_fbc_check_plane()
1563 		plane_state->no_fbc_reason = "plane end Y offset misaligned";  in intel_fbc_check_plane()
1589 				    struct intel_plane *plane)  in intel_fbc_can_flip_nuke()  argument
1594 		intel_atomic_get_old_plane_state(state, plane);  in intel_fbc_can_flip_nuke()
1596 		intel_atomic_get_new_plane_state(state, plane);  in intel_fbc_can_flip_nuke()
1634 				   struct intel_plane *plane)  in __intel_fbc_pre_update()  argument
1637 	struct intel_fbc *fbc = plane->fbc;  in __intel_fbc_pre_update()
1644 	if (intel_fbc_can_flip_nuke(state, crtc, plane))  in __intel_fbc_pre_update()
1651 	 * Need an extra vblank wait between FBC disable and most plane  in __intel_fbc_pre_update()
1652 	 * updates. Bspec says this is only needed for plane disable, but  in __intel_fbc_pre_update()
1653 	 * that is not true. Touching most plane registers will cause the  in __intel_fbc_pre_update()
1659 	 * and skipping the extra vblank wait before the plane update  in __intel_fbc_pre_update()
1674 	struct intel_plane *plane;  in intel_fbc_pre_update()  local
1677 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {  in intel_fbc_pre_update()
1678 		struct intel_fbc *fbc = plane->fbc;  in intel_fbc_pre_update()
1680 		if (!fbc || plane->pipe != crtc->pipe)  in intel_fbc_pre_update()
1685 		if (fbc->state.plane == plane)  in intel_fbc_pre_update()
1686 			need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);  in intel_fbc_pre_update()
1697 	struct intel_plane *plane = fbc->state.plane;  in __intel_fbc_disable()  local
1702 	drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n",  in __intel_fbc_disable()
1703 		    plane->base.base.id, plane->base.name);  in __intel_fbc_disable()
1713 	fbc->state.plane = NULL;  in __intel_fbc_disable()
1732 	struct intel_plane *plane;  in intel_fbc_post_update()  local
1735 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {  in intel_fbc_post_update()
1736 		struct intel_fbc *fbc = plane->fbc;  in intel_fbc_post_update()
1738 		if (!fbc || plane->pipe != crtc->pipe)  in intel_fbc_post_update()
1743 		if (fbc->state.plane == plane)  in intel_fbc_post_update()
1752 	if (fbc->state.plane)  in intel_fbc_get_frontbuffer_bit()
1753 		return fbc->state.plane->frontbuffer_bit;  in intel_fbc_get_frontbuffer_bit()
1831 	struct intel_plane *plane;  in intel_fbc_atomic_check()  local
1834 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {  in intel_fbc_atomic_check()
1837 		ret = intel_fbc_check_plane(state, plane);  in intel_fbc_atomic_check()
1847 			       struct intel_plane *plane)  in __intel_fbc_enable()  argument
1851 		intel_atomic_get_new_plane_state(state, plane);  in __intel_fbc_enable()
1852 	struct intel_fbc *fbc = plane->fbc;  in __intel_fbc_enable()
1856 	if (fbc->state.plane) {  in __intel_fbc_enable()
1857 		if (fbc->state.plane != plane)  in __intel_fbc_enable()
1861 			intel_fbc_update_state(state, crtc, plane);  in __intel_fbc_enable()
1890 	drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n",  in __intel_fbc_enable()
1891 		    plane->base.base.id, plane->base.name);  in __intel_fbc_enable()
1894 	intel_fbc_update_state(state, crtc, plane);  in __intel_fbc_enable()
1912 	struct intel_plane *plane;  in intel_fbc_disable()  local
1914 	for_each_intel_plane(display->drm, plane) {  in intel_fbc_disable()
1915 		struct intel_fbc *fbc = plane->fbc;  in intel_fbc_disable()
1917 		if (!fbc || plane->pipe != crtc->pipe)  in intel_fbc_disable()
1921 		if (fbc->state.plane == plane)  in intel_fbc_disable()
1933 	struct intel_plane *plane;  in intel_fbc_update()  local
1936 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {  in intel_fbc_update()
1937 		struct intel_fbc *fbc = plane->fbc;  in intel_fbc_update()
1939 		if (!fbc || plane->pipe != crtc->pipe)  in intel_fbc_update()
1946 			if (fbc->state.plane == plane)  in intel_fbc_update()
1949 			__intel_fbc_enable(state, crtc, plane);  in intel_fbc_update()
1964 	if (fbc->underrun_detected || !fbc->state.plane)  in intel_fbc_underrun_work_fn()
1972 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));  in intel_fbc_underrun_work_fn()
2076 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)  in intel_fbc_add_plane()  argument
2078 	plane->fbc = fbc;  in intel_fbc_add_plane()
2152 	struct intel_plane *plane;  in intel_fbc_debugfs_status_show()  local
2168 	for_each_intel_plane(display->drm, plane) {  in intel_fbc_debugfs_status_show()
2170 			to_intel_plane_state(plane->base.state);  in intel_fbc_debugfs_status_show()
2172 		if (plane->fbc != fbc)  in intel_fbc_debugfs_status_show()
2175 		seq_printf(m, "%c [PLANE:%d:%s]: %s\n",  in intel_fbc_debugfs_status_show()
2176 			   fbc->state.plane == plane ? '*' : ' ',  in intel_fbc_debugfs_status_show()
2177 			   plane->base.base.id, plane->base.name,  in intel_fbc_debugfs_status_show()
2234 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);  in intel_fbc_crtc_debugfs_add()  local
2236 	if (plane->fbc)  in intel_fbc_crtc_debugfs_add()
2237 		intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);  in intel_fbc_crtc_debugfs_add()