27  * "The Color Control Surface (CCS) contains the compression status of
29  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
31  *  cache-line-pairs. CCS is always Y tiled."
34  * each cache line in the CCS corresponds to an area of 32x16 cache
36  * us a ratio of one byte in the CCS for each 8x16 pixels in the
59  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
60  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
62  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
233 	} ccs;  member
259 		.ccs.packed_aux_planes = BIT(1),
260 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
268 		.ccs.packed_aux_planes = BIT(1),
276 		.ccs.cc_planes = BIT(2),
277 		.ccs.packed_aux_planes = BIT(1),
289 		.ccs.cc_planes = BIT(1),
305 		.ccs.packed_aux_planes = BIT(1),
306 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
314 		.ccs.packed_aux_planes = BIT(1),
322 		.ccs.cc_planes = BIT(2),
323 		.ccs.packed_aux_planes = BIT(1),
331 		.ccs.packed_aux_planes = BIT(1),
339 		.ccs.packed_aux_planes = BIT(1),
465  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
479  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
492  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
553 	 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms  in plane_has_modifier()
557 	    HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)  in plane_has_modifier()
631 	if (hweight8(md->ccs.planar_aux_planes) == 2)  in format_is_yuv_semiplanar()
655 		return md->ccs.planar_aux_planes;  in ccs_aux_plane_mask()
657 		return md->ccs.packed_aux_planes;  in ccs_aux_plane_mask()
661  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
666  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
676  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
681  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
692  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
703 	if (!md->ccs.cc_planes)  in intel_fb_rc_ccs_cc_plane()
706 	drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);  in intel_fb_rc_ccs_cc_plane()
708 	return ilog2((int)md->ccs.cc_planes);  in intel_fb_rc_ccs_cc_plane()
756 	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)  in skl_main_to_aux_plane()
863  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
918 	 * TODO: Deduct the subsampling from the char block for all CCS  in intel_fb_plane_get_subsampling()
935 	 * first plane. That's incorrect for the CCS AUX plane of the first  in intel_fb_plane_get_subsampling()
1198 	 * here the main and CCS coordinates must match only within a (64 byte  in intel_fb_check_ccs_xy()
1215 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile  in intel_fb_check_ccs_xy()
1216 	 * x/y offsets must match between CCS and the main surface.  in intel_fb_check_ccs_xy()
1220 			      "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",  in intel_fb_check_ccs_xy()
1253 	 * The new CCS hash mode isn't compatible with remapping as  in intel_plane_can_remap()
1547 			 * The hardware automagically calculates the CCS AUX surface  in calc_plane_remap_info()
1832 	 * The new CCS hash mode makes remapping impossible  in intel_fb_max_stride()
1869 		 * one 64 byte cacheline on the CCS AUX surface.  in intel_fb_stride_alignment()
2130 					    "ccs aux plane %d pitch (%d) must be %d\n",  in intel_framebuffer_init()