Lines Matching full:i915
67 void (*enable)(struct drm_i915_private *i915,
76 void (*disable)(struct drm_i915_private *i915,
84 bool (*get_hw_state)(struct drm_i915_private *i915,
92 int (*get_freq)(struct drm_i915_private *i915,
111 void (*update_ref_clks)(struct drm_i915_private *i915);
119 intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, in intel_atomic_duplicate_dpll_state() argument
126 for_each_shared_dpll(i915, pll, i) in intel_atomic_duplicate_dpll_state()
149 * @i915: i915 device instance
156 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, in intel_get_shared_dpll_by_id() argument
162 for_each_shared_dpll(i915, pll, i) { in intel_get_shared_dpll_by_id()
172 void assert_shared_dpll(struct drm_i915_private *i915, in assert_shared_dpll() argument
179 if (drm_WARN(&i915->drm, !pll, in assert_shared_dpll()
183 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); in assert_shared_dpll()
184 I915_STATE_WARN(i915, cur_state != state, in assert_shared_dpll()
201 intel_combo_pll_enable_reg(struct drm_i915_private *i915, in intel_combo_pll_enable_reg() argument
204 if (IS_DG1(i915)) in intel_combo_pll_enable_reg()
206 else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in intel_combo_pll_enable_reg()
214 intel_tc_pll_enable_reg(struct drm_i915_private *i915, in intel_tc_pll_enable_reg() argument
220 if (IS_ALDERLAKE_P(i915)) in intel_tc_pll_enable_reg()
226 static void _intel_enable_shared_dpll(struct drm_i915_private *i915, in _intel_enable_shared_dpll() argument
230 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in _intel_enable_shared_dpll()
232 pll->info->funcs->enable(i915, pll, &pll->state.hw_state); in _intel_enable_shared_dpll()
236 static void _intel_disable_shared_dpll(struct drm_i915_private *i915, in _intel_disable_shared_dpll() argument
239 pll->info->funcs->disable(i915, pll); in _intel_disable_shared_dpll()
243 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); in _intel_disable_shared_dpll()
255 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_enable_shared_dpll() local
260 if (drm_WARN_ON(&i915->drm, pll == NULL)) in intel_enable_shared_dpll()
263 mutex_lock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
266 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
267 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
272 drm_dbg_kms(&i915->drm, in intel_enable_shared_dpll()
278 drm_WARN_ON(&i915->drm, !pll->on); in intel_enable_shared_dpll()
279 assert_shared_dpll_enabled(i915, pll); in intel_enable_shared_dpll()
282 drm_WARN_ON(&i915->drm, pll->on); in intel_enable_shared_dpll()
284 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); in intel_enable_shared_dpll()
286 _intel_enable_shared_dpll(i915, pll); in intel_enable_shared_dpll()
289 mutex_unlock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
301 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_disable_shared_dpll() local
306 if (DISPLAY_VER(i915) < 5) in intel_disable_shared_dpll()
312 mutex_lock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
313 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
318 drm_dbg_kms(&i915->drm, in intel_disable_shared_dpll()
323 assert_shared_dpll_enabled(i915, pll); in intel_disable_shared_dpll()
324 drm_WARN_ON(&i915->drm, !pll->on); in intel_disable_shared_dpll()
330 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); in intel_disable_shared_dpll()
332 _intel_disable_shared_dpll(i915, pll); in intel_disable_shared_dpll()
335 mutex_unlock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
339 intel_dpll_mask_all(struct drm_i915_private *i915) in intel_dpll_mask_all() argument
345 for_each_shared_dpll(i915, pll, i) { in intel_dpll_mask_all()
346 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); in intel_dpll_mask_all()
360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_find_shared_dpll() local
361 unsigned long dpll_mask_all = intel_dpll_mask_all(i915); in intel_find_shared_dpll()
368 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); in intel_find_shared_dpll()
373 pll = intel_get_shared_dpll_by_id(i915, id); in intel_find_shared_dpll()
387 drm_dbg_kms(&i915->drm, in intel_find_shared_dpll()
399 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", in intel_find_shared_dpll()
421 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_reference_shared_dpll_crtc() local
423 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); in intel_reference_shared_dpll_crtc()
427 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n", in intel_reference_shared_dpll_crtc()
460 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_unreference_shared_dpll_crtc() local
462 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); in intel_unreference_shared_dpll_crtc()
466 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n", in intel_unreference_shared_dpll_crtc()
510 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_swap_state() local
518 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_swap_state()
522 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, in ibx_pch_dpll_get_hw_state() argument
531 wakeref = intel_display_power_get_if_enabled(i915, in ibx_pch_dpll_get_hw_state()
536 val = intel_de_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
538 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
539 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
541 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in ibx_pch_dpll_get_hw_state()
546 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) in ibx_assert_pch_refclk_enabled() argument
551 val = intel_de_read(i915, PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
554 I915_STATE_WARN(i915, !enabled, in ibx_assert_pch_refclk_enabled()
558 static void ibx_pch_dpll_enable(struct drm_i915_private *i915, in ibx_pch_dpll_enable() argument
566 ibx_assert_pch_refclk_enabled(i915); in ibx_pch_dpll_enable()
568 intel_de_write(i915, PCH_FP0(id), hw_state->fp0); in ibx_pch_dpll_enable()
569 intel_de_write(i915, PCH_FP1(id), hw_state->fp1); in ibx_pch_dpll_enable()
571 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
574 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
582 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
583 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
587 static void ibx_pch_dpll_disable(struct drm_i915_private *i915, in ibx_pch_dpll_disable() argument
592 intel_de_write(i915, PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
593 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_disable()
610 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ibx_get_dpll() local
614 if (HAS_PCH_IBX(i915)) { in ibx_get_dpll()
617 pll = intel_get_shared_dpll_by_id(i915, id); in ibx_get_dpll()
619 drm_dbg_kms(&i915->drm, in ibx_get_dpll()
688 static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, in hsw_ddi_wrpll_enable() argument
695 intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll); in hsw_ddi_wrpll_enable()
696 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
700 static void hsw_ddi_spll_enable(struct drm_i915_private *i915, in hsw_ddi_spll_enable() argument
706 intel_de_write(i915, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
707 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_enable()
711 static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, in hsw_ddi_wrpll_disable() argument
716 intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); in hsw_ddi_wrpll_disable()
717 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
723 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
724 intel_init_pch_refclk(i915); in hsw_ddi_wrpll_disable()
727 static void hsw_ddi_spll_disable(struct drm_i915_private *i915, in hsw_ddi_spll_disable() argument
732 intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); in hsw_ddi_spll_disable()
733 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_disable()
739 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
740 intel_init_pch_refclk(i915); in hsw_ddi_spll_disable()
743 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_wrpll_get_hw_state() argument
752 wakeref = intel_display_power_get_if_enabled(i915, in hsw_ddi_wrpll_get_hw_state()
757 val = intel_de_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
760 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in hsw_ddi_wrpll_get_hw_state()
765 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_spll_get_hw_state() argument
773 wakeref = intel_display_power_get_if_enabled(i915, in hsw_ddi_spll_get_hw_state()
778 val = intel_de_read(i915, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
781 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in hsw_ddi_spll_get_hw_state()
992 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, in hsw_ddi_wrpll_get_freq() argument
1004 if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) { in hsw_ddi_wrpll_get_freq()
1005 refclk = i915->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
1015 refclk = i915->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1037 struct drm_i915_private *i915 = to_i915(state->base.dev); in hsw_ddi_wrpll_compute_dpll() local
1050 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1072 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_compute_dpll() local
1081 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", in hsw_ddi_lcpll_compute_dpll()
1090 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_get_dpll() local
1110 pll = intel_get_shared_dpll_by_id(i915, pll_id); in hsw_ddi_lcpll_get_dpll()
1118 static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, in hsw_ddi_lcpll_get_freq() argument
1135 drm_WARN(&i915->drm, 1, "bad port clock sel\n"); in hsw_ddi_lcpll_get_freq()
1170 static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, in hsw_ddi_spll_get_freq() argument
1188 drm_WARN(&i915->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1238 static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) in hsw_update_dpll_ref_clks() argument
1240 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1242 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1243 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1245 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1281 static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, in hsw_ddi_lcpll_enable() argument
1287 static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, in hsw_ddi_lcpll_disable() argument
1292 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, in hsw_ddi_lcpll_get_hw_state() argument
1360 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, in skl_ddi_pll_write_ctrl1() argument
1366 intel_de_rmw(i915, DPLL_CTRL1, in skl_ddi_pll_write_ctrl1()
1371 intel_de_posting_read(i915, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1374 static void skl_ddi_pll_enable(struct drm_i915_private *i915, in skl_ddi_pll_enable() argument
1382 skl_ddi_pll_write_ctrl1(i915, pll, hw_state); in skl_ddi_pll_enable()
1384 intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1); in skl_ddi_pll_enable()
1385 intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2); in skl_ddi_pll_enable()
1386 intel_de_posting_read(i915, regs[id].cfgcr1); in skl_ddi_pll_enable()
1387 intel_de_posting_read(i915, regs[id].cfgcr2); in skl_ddi_pll_enable()
1390 intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
1392 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) in skl_ddi_pll_enable()
1393 drm_err(&i915->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1396 static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, in skl_ddi_dpll0_enable() argument
1402 skl_ddi_pll_write_ctrl1(i915, pll, hw_state); in skl_ddi_dpll0_enable()
1405 static void skl_ddi_pll_disable(struct drm_i915_private *i915, in skl_ddi_pll_disable() argument
1412 intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); in skl_ddi_pll_disable()
1413 intel_de_posting_read(i915, regs[id].ctl); in skl_ddi_pll_disable()
1416 static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, in skl_ddi_dpll0_disable() argument
1421 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, in skl_ddi_pll_get_hw_state() argument
1432 wakeref = intel_display_power_get_if_enabled(i915, in skl_ddi_pll_get_hw_state()
1439 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1443 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1448 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1449 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1454 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in skl_ddi_pll_get_hw_state()
1459 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, in skl_ddi_dpll0_get_hw_state() argument
1470 wakeref = intel_display_power_get_if_enabled(i915, in skl_ddi_dpll0_get_hw_state()
1478 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_dpll0_get_hw_state()
1479 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) in skl_ddi_dpll0_get_hw_state()
1482 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
1488 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in skl_ddi_dpll0_get_hw_state()
1732 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, in skl_ddi_wrpll_get_freq() argument
1737 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1764 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); in skl_ddi_wrpll_get_freq()
1798 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in skl_ddi_wrpll_get_freq()
1806 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_ddi_hdmi_pll_dividers() local
1812 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1836 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1880 static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, in skl_ddi_lcpll_get_freq() argument
1908 drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); in skl_ddi_lcpll_get_freq()
1959 static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, in skl_ddi_pll_get_freq() argument
1970 return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state); in skl_ddi_pll_get_freq()
1972 return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state); in skl_ddi_pll_get_freq()
1975 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) in skl_update_dpll_ref_clks() argument
1978 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
2034 static void bxt_ddi_pll_enable(struct drm_i915_private *i915, in bxt_ddi_pll_enable() argument
2044 bxt_port_to_phy_channel(i915, port, &phy, &ch); in bxt_ddi_pll_enable()
2047 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); in bxt_ddi_pll_enable()
2049 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_enable()
2050 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_enable()
2053 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_enable()
2055 drm_err(&i915->drm, in bxt_ddi_pll_enable()
2060 intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), in bxt_ddi_pll_enable()
2064 intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), in bxt_ddi_pll_enable()
2068 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0), in bxt_ddi_pll_enable()
2072 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1), in bxt_ddi_pll_enable()
2076 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2), in bxt_ddi_pll_enable()
2080 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3), in bxt_ddi_pll_enable()
2084 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_enable()
2089 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp); in bxt_ddi_pll_enable()
2092 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8), in bxt_ddi_pll_enable()
2095 intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9), in bxt_ddi_pll_enable()
2098 temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_enable()
2102 intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp); in bxt_ddi_pll_enable()
2105 temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_enable()
2107 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
2110 intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
2113 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); in bxt_ddi_pll_enable()
2114 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_enable()
2116 if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), in bxt_ddi_pll_enable()
2118 drm_err(&i915->drm, "PLL %d not locked\n", port); in bxt_ddi_pll_enable()
2120 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_enable()
2121 temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0)); in bxt_ddi_pll_enable()
2123 intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp); in bxt_ddi_pll_enable()
2130 temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); in bxt_ddi_pll_enable()
2134 intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); in bxt_ddi_pll_enable()
2137 static void bxt_ddi_pll_disable(struct drm_i915_private *i915, in bxt_ddi_pll_disable() argument
2142 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); in bxt_ddi_pll_disable()
2143 intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_disable()
2145 if (IS_GEMINILAKE(i915)) { in bxt_ddi_pll_disable()
2146 intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_disable()
2149 if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & in bxt_ddi_pll_disable()
2151 drm_err(&i915->drm, in bxt_ddi_pll_disable()
2156 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, in bxt_ddi_pll_get_hw_state() argument
2168 bxt_port_to_phy_channel(i915, port, &phy, &ch); in bxt_ddi_pll_get_hw_state()
2170 wakeref = intel_display_power_get_if_enabled(i915, in bxt_ddi_pll_get_hw_state()
2177 val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)); in bxt_ddi_pll_get_hw_state()
2181 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2184 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2187 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2190 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2193 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2196 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2199 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2204 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2207 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2210 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2219 hw_state->pcsdw12 = intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2221 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2222 drm_dbg(&i915->drm, in bxt_ddi_pll_get_hw_state()
2225 intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2232 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in bxt_ddi_pll_get_hw_state()
2253 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_pll_dividers() local
2263 drm_WARN_ON(&i915->drm, clk_div->m1 != 2); in bxt_ddi_hdmi_pll_dividers()
2271 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_dp_pll_dividers() local
2282 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2284 drm_WARN_ON(&i915->drm, clk_div->vco == 0 || in bxt_ddi_dp_pll_dividers()
2291 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_set_dpll_hw_state() local
2315 drm_err(&i915->drm, "Invalid VCO\n"); in bxt_ddi_set_dpll_hw_state()
2356 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, in bxt_ddi_pll_get_freq() argument
2372 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2388 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_set_dpll_hw_state() local
2398 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2425 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in bxt_get_dpll() local
2431 pll = intel_get_shared_dpll_by_id(i915, id); in bxt_get_dpll()
2433 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", in bxt_get_dpll()
2444 static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) in bxt_update_dpll_ref_clks() argument
2446 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2447 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2599 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) in ehl_combo_pll_div_frac_wa_needed() argument
2601 return ((IS_ELKHARTLAKE(i915) && in ehl_combo_pll_div_frac_wa_needed()
2602 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || in ehl_combo_pll_div_frac_wa_needed()
2603 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && in ehl_combo_pll_div_frac_wa_needed()
2604 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2696 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_dp_combo_pll() local
2698 i915->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2718 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_tbt_pll() local
2720 if (DISPLAY_VER(i915) >= 12) { in icl_calc_tbt_pll()
2721 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2723 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2734 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2736 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2751 static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_tbt_pll_get_freq() argument
2759 drm_WARN_ON(&i915->drm, 1); in icl_ddi_tbt_pll_get_freq()
2764 static int icl_wrpll_ref_clock(struct drm_i915_private *i915) in icl_wrpll_ref_clock() argument
2766 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2782 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_wrpll() local
2783 int ref_clock = icl_wrpll_ref_clock(i915); in icl_calc_wrpll()
2822 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_combo_pll_get_freq() argument
2827 int ref_clock = icl_wrpll_ref_clock(i915); in icl_ddi_combo_pll_get_freq()
2873 if (ehl_combo_pll_div_frac_wa_needed(i915)) in icl_ddi_combo_pll_get_freq()
2878 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in icl_ddi_combo_pll_get_freq()
2884 static void icl_calc_dpll_state(struct drm_i915_private *i915, in icl_calc_dpll_state() argument
2891 if (ehl_combo_pll_div_frac_wa_needed(i915)) in icl_calc_dpll_state()
2902 if (DISPLAY_VER(i915) >= 12) in icl_calc_dpll_state()
2907 if (i915->display.vbt.override_afc_startup) in icl_calc_dpll_state()
2908 hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); in icl_calc_dpll_state()
2994 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_mg_pll_state() local
2996 int refclk_khz = i915->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3006 bool is_dkl = DISPLAY_VER(i915) >= 12; in icl_calc_mg_pll_state()
3104 if (i915->display.vbt.override_afc_startup) { in icl_calc_mg_pll_state()
3105 u8 val = i915->display.vbt.override_afc_startup_val; in icl_calc_mg_pll_state()
3195 static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, in icl_ddi_mg_pll_get_freq() argument
3203 ref_clock = i915->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3205 if (DISPLAY_VER(i915) >= 12) { in icl_ddi_mg_pll_get_freq()
3310 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_compute_combo_phy_dpll() local
3327 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3332 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, in icl_compute_combo_phy_dpll()
3343 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_get_combo_phy_dpll() local
3351 if (IS_ALDERLAKE_S(i915)) { in icl_get_combo_phy_dpll()
3357 } else if (IS_DG1(i915)) { in icl_get_combo_phy_dpll()
3367 } else if (IS_ROCKETLAKE(i915)) { in icl_get_combo_phy_dpll()
3372 } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_get_combo_phy_dpll()
3402 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_tc_phy_dplls() local
3417 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3431 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, in icl_compute_tc_phy_dplls()
3535 static bool mg_pll_get_hw_state(struct drm_i915_private *i915, in mg_pll_get_hw_state() argument
3546 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_get_hw_state()
3548 wakeref = intel_display_power_get_if_enabled(i915, in mg_pll_get_hw_state()
3553 val = intel_de_read(i915, enable_reg); in mg_pll_get_hw_state()
3557 hw_state->mg_refclkin_ctl = intel_de_read(i915, in mg_pll_get_hw_state()
3562 intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state()
3567 intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state()
3574 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3575 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3576 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3577 hw_state->mg_pll_frac_lock = intel_de_read(i915, in mg_pll_get_hw_state()
3579 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3581 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3583 intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); in mg_pll_get_hw_state()
3585 if (i915->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3598 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in mg_pll_get_hw_state()
3602 static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, in dkl_pll_get_hw_state() argument
3613 wakeref = intel_display_power_get_if_enabled(i915, in dkl_pll_get_hw_state()
3618 val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); in dkl_pll_get_hw_state()
3626 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, in dkl_pll_get_hw_state()
3631 intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); in dkl_pll_get_hw_state()
3639 intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); in dkl_pll_get_hw_state()
3643 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3645 if (i915->display.vbt.override_afc_startup) in dkl_pll_get_hw_state()
3649 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3653 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3659 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3664 intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_get_hw_state()
3670 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in dkl_pll_get_hw_state()
3674 static bool icl_pll_get_hw_state(struct drm_i915_private *i915, in icl_pll_get_hw_state() argument
3685 wakeref = intel_display_power_get_if_enabled(i915, in icl_pll_get_hw_state()
3690 val = intel_de_read(i915, enable_reg); in icl_pll_get_hw_state()
3694 if (IS_ALDERLAKE_S(i915)) { in icl_pll_get_hw_state()
3695 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3696 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3697 } else if (IS_DG1(i915)) { in icl_pll_get_hw_state()
3698 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3699 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3700 } else if (IS_ROCKETLAKE(i915)) { in icl_pll_get_hw_state()
3701 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3703 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3705 } else if (DISPLAY_VER(i915) >= 12) { in icl_pll_get_hw_state()
3706 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3708 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3710 if (i915->display.vbt.override_afc_startup) { in icl_pll_get_hw_state()
3711 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3715 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_pll_get_hw_state()
3717 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3719 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3722 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3724 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3731 intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); in icl_pll_get_hw_state()
3735 static bool combo_pll_get_hw_state(struct drm_i915_private *i915, in combo_pll_get_hw_state() argument
3739 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_get_hw_state()
3741 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg); in combo_pll_get_hw_state()
3744 static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, in tbt_pll_get_hw_state() argument
3748 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE); in tbt_pll_get_hw_state()
3751 static void icl_dpll_write(struct drm_i915_private *i915, in icl_dpll_write() argument
3758 if (IS_ALDERLAKE_S(i915)) { in icl_dpll_write()
3761 } else if (IS_DG1(i915)) { in icl_dpll_write()
3764 } else if (IS_ROCKETLAKE(i915)) { in icl_dpll_write()
3767 } else if (DISPLAY_VER(i915) >= 12) { in icl_dpll_write()
3772 if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && in icl_dpll_write()
3782 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3783 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3784 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && in icl_dpll_write()
3786 if (i915->display.vbt.override_afc_startup && in icl_dpll_write()
3788 intel_de_rmw(i915, div0_reg, in icl_dpll_write()
3790 intel_de_posting_read(i915, cfgcr1_reg); in icl_dpll_write()
3793 static void icl_mg_pll_write(struct drm_i915_private *i915, in icl_mg_pll_write() argument
3805 intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port), in icl_mg_pll_write()
3808 intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port), in icl_mg_pll_write()
3812 intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port), in icl_mg_pll_write()
3819 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3820 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3821 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3822 intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port), in icl_mg_pll_write()
3824 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3826 intel_de_rmw(i915, MG_PLL_BIAS(tc_port), in icl_mg_pll_write()
3829 intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port), in icl_mg_pll_write()
3833 intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); in icl_mg_pll_write()
3836 static void dkl_pll_write(struct drm_i915_private *i915, in dkl_pll_write() argument
3848 val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); in dkl_pll_write()
3851 intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val); in dkl_pll_write()
3853 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); in dkl_pll_write()
3856 intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); in dkl_pll_write()
3858 val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); in dkl_pll_write()
3864 intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val); in dkl_pll_write()
3867 if (i915->display.vbt.override_afc_startup) in dkl_pll_write()
3869 intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, in dkl_pll_write()
3872 val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_write()
3876 intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val); in dkl_pll_write()
3878 val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_write()
3884 intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val); in dkl_pll_write()
3886 val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_write()
3890 intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val); in dkl_pll_write()
3892 val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_write()
3896 intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); in dkl_pll_write()
3898 intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); in dkl_pll_write()
3901 static void icl_pll_power_enable(struct drm_i915_private *i915, in icl_pll_power_enable() argument
3905 intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE); in icl_pll_power_enable()
3911 if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_power_enable()
3912 drm_err(&i915->drm, "PLL %d Power not enabled\n", in icl_pll_power_enable()
3916 static void icl_pll_enable(struct drm_i915_private *i915, in icl_pll_enable() argument
3920 intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE); in icl_pll_enable()
3923 if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1)) in icl_pll_enable()
3924 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); in icl_pll_enable()
3927 static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) in adlp_cmtg_clock_gating_wa() argument
3931 if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) || in adlp_cmtg_clock_gating_wa()
3945 val = intel_de_read(i915, TRANS_CMTG_CHICKEN); in adlp_cmtg_clock_gating_wa()
3946 val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING); in adlp_cmtg_clock_gating_wa()
3947 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING)) in adlp_cmtg_clock_gating_wa()
3948 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); in adlp_cmtg_clock_gating_wa()
3951 static void combo_pll_enable(struct drm_i915_private *i915, in combo_pll_enable() argument
3956 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_enable()
3958 icl_pll_power_enable(i915, pll, enable_reg); in combo_pll_enable()
3960 icl_dpll_write(i915, pll, hw_state); in combo_pll_enable()
3968 icl_pll_enable(i915, pll, enable_reg); in combo_pll_enable()
3970 adlp_cmtg_clock_gating_wa(i915, pll); in combo_pll_enable()
3975 static void tbt_pll_enable(struct drm_i915_private *i915, in tbt_pll_enable() argument
3981 icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3983 icl_dpll_write(i915, pll, hw_state); in tbt_pll_enable()
3991 icl_pll_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3996 static void mg_pll_enable(struct drm_i915_private *i915, in mg_pll_enable() argument
4001 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_enable()
4003 icl_pll_power_enable(i915, pll, enable_reg); in mg_pll_enable()
4005 if (DISPLAY_VER(i915) >= 12) in mg_pll_enable()
4006 dkl_pll_write(i915, pll, hw_state); in mg_pll_enable()
4008 icl_mg_pll_write(i915, pll, hw_state); in mg_pll_enable()
4016 icl_pll_enable(i915, pll, enable_reg); in mg_pll_enable()
4021 static void icl_pll_disable(struct drm_i915_private *i915, in icl_pll_disable() argument
4033 intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); in icl_pll_disable()
4036 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1)) in icl_pll_disable()
4037 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); in icl_pll_disable()
4041 intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0); in icl_pll_disable()
4047 if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_disable()
4048 drm_err(&i915->drm, "PLL %d Power not disabled\n", in icl_pll_disable()
4052 static void combo_pll_disable(struct drm_i915_private *i915, in combo_pll_disable() argument
4055 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_disable()
4057 icl_pll_disable(i915, pll, enable_reg); in combo_pll_disable()
4060 static void tbt_pll_disable(struct drm_i915_private *i915, in tbt_pll_disable() argument
4063 icl_pll_disable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_disable()
4066 static void mg_pll_disable(struct drm_i915_private *i915, in mg_pll_disable() argument
4069 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_disable()
4071 icl_pll_disable(i915, pll, enable_reg); in mg_pll_disable()
4074 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) in icl_update_dpll_ref_clks() argument
4077 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
4298 * @i915: i915 device
4300 * Initialize shared DPLLs for @i915.
4302 void intel_shared_dpll_init(struct drm_i915_private *i915) in intel_shared_dpll_init() argument
4308 mutex_init(&i915->display.dpll.lock); in intel_shared_dpll_init()
4310 if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915)) in intel_shared_dpll_init()
4313 else if (IS_ALDERLAKE_P(i915)) in intel_shared_dpll_init()
4315 else if (IS_ALDERLAKE_S(i915)) in intel_shared_dpll_init()
4317 else if (IS_DG1(i915)) in intel_shared_dpll_init()
4319 else if (IS_ROCKETLAKE(i915)) in intel_shared_dpll_init()
4321 else if (DISPLAY_VER(i915) >= 12) in intel_shared_dpll_init()
4323 else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) in intel_shared_dpll_init()
4325 else if (DISPLAY_VER(i915) >= 11) in intel_shared_dpll_init()
4327 else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) in intel_shared_dpll_init()
4329 else if (DISPLAY_VER(i915) == 9) in intel_shared_dpll_init()
4331 else if (HAS_DDI(i915)) in intel_shared_dpll_init()
4333 else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) in intel_shared_dpll_init()
4342 if (drm_WARN_ON(&i915->drm, in intel_shared_dpll_init()
4343 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4347 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) in intel_shared_dpll_init()
4350 i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4351 i915->display.dpll.shared_dplls[i].index = i; in intel_shared_dpll_init()
4354 i915->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4355 i915->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4376 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_compute_shared_dplls() local
4377 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_compute_shared_dplls()
4379 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_compute_shared_dplls()
4409 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_reserve_shared_dplls() local
4410 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_reserve_shared_dplls()
4412 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_reserve_shared_dplls()
4432 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_release_shared_dplls() local
4433 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_release_shared_dplls()
4461 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_update_active_dpll() local
4462 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_update_active_dpll()
4464 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_update_active_dpll()
4472 * @i915: i915 device
4478 int intel_dpll_get_freq(struct drm_i915_private *i915, in intel_dpll_get_freq() argument
4482 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) in intel_dpll_get_freq()
4485 return pll->info->funcs->get_freq(i915, pll, dpll_hw_state); in intel_dpll_get_freq()
4490 * @i915: i915 device
4496 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, in intel_dpll_get_hw_state() argument
4500 return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state); in intel_dpll_get_hw_state()
4503 static void readout_dpll_hw_state(struct drm_i915_private *i915, in readout_dpll_hw_state() argument
4508 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4511 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in readout_dpll_hw_state()
4514 for_each_intel_crtc(&i915->drm, crtc) { in readout_dpll_hw_state()
4523 drm_dbg_kms(&i915->drm, in readout_dpll_hw_state()
4528 void intel_dpll_update_ref_clks(struct drm_i915_private *i915) in intel_dpll_update_ref_clks() argument
4530 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4531 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4534 void intel_dpll_readout_hw_state(struct drm_i915_private *i915) in intel_dpll_readout_hw_state() argument
4539 for_each_shared_dpll(i915, pll, i) in intel_dpll_readout_hw_state()
4540 readout_dpll_hw_state(i915, pll); in intel_dpll_readout_hw_state()
4543 static void sanitize_dpll_state(struct drm_i915_private *i915, in sanitize_dpll_state() argument
4549 adlp_cmtg_clock_gating_wa(i915, pll); in sanitize_dpll_state()
4554 drm_dbg_kms(&i915->drm, in sanitize_dpll_state()
4558 _intel_disable_shared_dpll(i915, pll); in sanitize_dpll_state()
4561 void intel_dpll_sanitize_state(struct drm_i915_private *i915) in intel_dpll_sanitize_state() argument
4566 for_each_shared_dpll(i915, pll, i) in intel_dpll_sanitize_state()
4567 sanitize_dpll_state(i915, pll); in intel_dpll_sanitize_state()
4572 * @i915: i915 drm device
4578 void intel_dpll_dump_hw_state(struct drm_i915_private *i915, in intel_dpll_dump_hw_state() argument
4582 if (i915->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4583 i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state); in intel_dpll_dump_hw_state()
4594 * @i915: i915 drm device
4602 bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, in intel_dpll_compare_hw_state() argument
4606 if (i915->display.dpll.mgr) { in intel_dpll_compare_hw_state()
4607 return i915->display.dpll.mgr->compare_hw_state(a, b); in intel_dpll_compare_hw_state()
4617 verify_single_dpll_state(struct drm_i915_private *i915, in verify_single_dpll_state() argument
4626 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); in verify_single_dpll_state()
4629 I915_STATE_WARN(i915, !pll->on && pll->active_mask, in verify_single_dpll_state()
4632 I915_STATE_WARN(i915, pll->on && !pll->active_mask, in verify_single_dpll_state()
4635 I915_STATE_WARN(i915, pll->on != active, in verify_single_dpll_state()
4641 I915_STATE_WARN(i915, in verify_single_dpll_state()
4652 I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), in verify_single_dpll_state()
4656 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in verify_single_dpll_state()
4660 I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4664 I915_STATE_WARN(i915, in verify_single_dpll_state()
4681 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_state_verify() local
4688 verify_single_dpll_state(i915, new_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4696 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in intel_shared_dpll_state_verify()
4701 I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4711 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_verify_disabled() local
4715 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_verify_disabled()
4716 verify_single_dpll_state(i915, pll, NULL, NULL); in intel_shared_dpll_verify_disabled()