Lines Matching full:dpll
85 * Hook for reading the values currently programmed to the DPLL
130 /* Copy dpll state */
154 * intel_get_dpll_by_id - get a DPLL given its id
159 * A pointer to the DPLL with @id
186 "asserting DPLL %s with no DPLL\n", str_on_off(state)))
253 * intel_dpll_enable - enable a CRTC's DPLL
254 * @crtc_state: CRTC, and its state, which has a DPLL
256 * Enable DPLL used by @crtc.
269 mutex_lock(&display->dpll.lock);
295 mutex_unlock(&display->dpll.lock);
299 * intel_dpll_disable - disable a CRTC's shared DPLL
300 * @crtc_state: CRTC, and its state, which has a shared DPLL
302 * Disable DPLL used by @crtc.
318 mutex_lock(&display->dpll.lock);
341 mutex_unlock(&display->dpll.lock);
415 * intel_dpll_crtc_get - Get a DPLL reference for a CRTC
417 * @pll: DPLL for which the reference is taken
418 * @dpll_state: the DPLL atomic state in which the reference is tracked
454 * intel_dpll_crtc_put - Drop a DPLL reference for a CRTC
456 * @pll: DPLL for which the reference is dropped
457 * @dpll_state: the DPLL atomic state in which the reference is tracked
504 * intel_dpll_swap_state - make atomic DPLL configuration effective
507 * This is the dpll version of drm_atomic_helper_swap_state() since the
543 hw_state->dpll = val;
577 intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
584 * DPLL is enabled and the clocks are stable.
588 intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
653 drm_printf(p, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
655 hw_state->dpll,
667 return a->dpll == b->dpll &&
680 { .name = "PCH DPLL A", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_A, },
681 { .name = "PCH DPLL B", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_B, },
729 if (display->dpll.pch_ssc_use & BIT(id))
745 if (display->dpll.pch_ssc_use & BIT(id))
1011 refclk = display->dpll.ref_clks.nssc;
1021 refclk = display->dpll.ref_clks.ssc;
1246 display->dpll.ref_clks.ssc = 135000;
1249 display->dpll.ref_clks.nssc = 24000;
1251 display->dpll.ref_clks.nssc = 135000;
1342 /* DPLL 0 */
1344 /* DPLL 0 doesn't support HDMI mode */
1347 /* DPLL 1 */
1353 /* DPLL 2 */
1359 /* DPLL 3 */
1399 drm_err(display->drm, "DPLL %d not locked\n", id);
1743 int ref_clock = display->dpll.ref_clks.nssc;
1818 display->dpll.ref_clks.nssc, &wrpll_params);
1824 * as the DPLL id in this function.
1856 * as the DPLL id in this function.
1984 display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
2022 { .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0,
2024 { .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
2025 { .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
2026 { .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, },
2244 static const struct dpll bxt_dp_clk_val[] = {
2257 struct dpll *clk_div)
2275 struct dpll *clk_div)
2288 chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);
2295 const struct dpll *clk_div)
2367 struct dpll clock;
2378 return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);
2384 struct dpll clk_div = {};
2395 struct dpll clk_div = {};
2452 display->dpll.ref_clks.ssc = 100000;
2453 display->dpll.ref_clks.nssc = 100000;
2610 display->dpll.ref_clks.nssc == 38400;
2704 display->dpll.ref_clks.nssc == 24000 ?
2727 switch (display->dpll.ref_clks.nssc) {
2729 MISSING_CASE(display->dpll.ref_clks.nssc);
2740 switch (display->dpll.ref_clks.nssc) {
2742 MISSING_CASE(display->dpll.ref_clks.nssc);
2772 int ref_clock = display->dpll.ref_clks.nssc;
2776 * use 19.2 because the DPLL automatically divides that by 2.
3002 int refclk_khz = display->dpll.ref_clks.nssc;
3209 ref_clock = display->dpll.ref_clks.nssc;
3275 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3276 * @crtc_state: state for the CRTC to select the DPLL for
3590 if (display->dpll.ref_clks.nssc == 38400) {
4082 display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
4153 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4154 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4176 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4177 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4178 { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4,
4201 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4202 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4226 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4227 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4228 { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, },
4243 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL0, },
4244 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL1, },
4245 { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
4246 { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
4261 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4262 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4263 { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, },
4264 { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, },
4279 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
4280 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
4313 mutex_init(&display->dpll.lock);
4348 i >= ARRAY_SIZE(display->dpll.dplls)))
4355 display->dpll.dplls[i].info = &dpll_info[i];
4356 display->dpll.dplls[i].index = i;
4359 display->dpll.mgr = dpll_mgr;
4360 display->dpll.num_dpll = i;
4364 * intel_dpll_compute - compute DPLL state CRTC and encoder combination
4369 * This function computes the DPLL state for the given CRTC and encoder.
4382 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
4415 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
4438 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
4443 * the DPLL framework and intel_dpll_reserve() is not
4453 * intel_dpll_update_active - update the active DPLL for a CRTC/encoder
4455 * @crtc: the CRTC for which to update the active DPLL
4456 * @encoder: encoder determining the type of port DPLL
4458 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4460 * DPLL selected will be based on the current mode of the encoder's port.
4467 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
4476 * intel_dpll_get_freq - calculate the DPLL's output frequency
4478 * @pll: DPLL for which to calculate the output frequency
4479 * @dpll_hw_state: DPLL state from which to calculate the output frequency
4494 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4496 * @pll: DPLL for which to calculate the output frequency
4497 * @dpll_hw_state: DPLL's hardware state
4535 if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)
4536 display->dpll.mgr->update_ref_clks(display);
4589 if (display->dpll.mgr) {
4590 display->dpll.mgr->dump_hw_state(p, dpll_hw_state);
4592 /* fallback for platforms that don't use the shared dpll
4602 * @a: first DPLL hw state
4603 * @b: second DPLL hw state
4605 * Compare DPLL hw states @a and @b.
4613 if (display->dpll.mgr) {
4614 return display->dpll.mgr->compare_hw_state(a, b);
4616 /* fallback for platforms that don't use the shared dpll