Lines Matching defs:pll
69 * Hook for enabling the pll, called from intel_enable_dpll() if
70 * the pll is not already enabled.
73 struct intel_dpll *pll,
77 * Hook for disabling the pll, called from intel_disable_dpll()
78 * only when it is safe to disable the pll, i.e., there are no more
82 struct intel_dpll *pll);
90 struct intel_dpll *pll,
94 * Hook for calculating the pll's output frequency based on its passed
98 const struct intel_dpll *pll,
127 struct intel_dpll *pll;
131 for_each_dpll(display, pll, i)
132 dpll_state[pll->index] = pll->state;
156 * @id: pll id
165 struct intel_dpll *pll;
168 for_each_dpll(display, pll, i) {
169 if (pll->info->id == id)
170 return pll;
179 struct intel_dpll *pll,
185 if (drm_WARN(display->drm, !pll,
189 cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
192 pll->info->name, str_on_off(state),
208 struct intel_dpll *pll)
211 return DG1_DPLL_ENABLE(pll->info->id);
213 (pll->info->id == DPLL_ID_EHL_DPLL4))
216 return ICL_DPLL_ENABLE(pll->info->id);
221 struct intel_dpll *pll)
223 const enum intel_dpll_id id = pll->info->id;
233 struct intel_dpll *pll)
235 if (pll->info->power_domain)
236 pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
238 pll->info->funcs->enable(display, pll, &pll->state.hw_state);
239 pll->on = true;
243 struct intel_dpll *pll)
245 pll->info->funcs->disable(display, pll);
246 pll->on = false;
248 if (pll->info->power_domain)
249 intel_display_power_put(display, pll->info->power_domain, pll->wakeref);
262 struct intel_dpll *pll = crtc_state->intel_dpll;
266 if (drm_WARN_ON(display->drm, !pll))
270 old_mask = pll->active_mask;
272 if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
273 drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
276 pll->active_mask |= pipe_mask;
280 pll->info->name, pll->active_mask, pll->on,
284 drm_WARN_ON(display->drm, !pll->on);
285 assert_dpll_enabled(display, pll);
288 drm_WARN_ON(display->drm, pll->on);
290 drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
292 _intel_enable_shared_dpll(display, pll);
308 struct intel_dpll *pll = crtc_state->intel_dpll;
315 if (pll == NULL)
319 if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
320 "%s not used by [CRTC:%d:%s]\n", pll->info->name,
326 pll->info->name, pll->active_mask, pll->on,
329 assert_dpll_enabled(display, pll);
330 drm_WARN_ON(display->drm, !pll->on);
332 pll->active_mask &= ~pipe_mask;
333 if (pll->active_mask)
336 drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
338 _intel_disable_shared_dpll(display, pll);
347 struct intel_dpll *pll;
351 for_each_dpll(display, pll, i) {
352 drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
354 dpll_mask |= BIT(pll->info->id);
377 struct intel_dpll *pll;
379 pll = intel_get_dpll_by_id(display, id);
380 if (!pll)
384 if (dpll_state[pll->index].pipe_mask == 0) {
386 unused_pll = pll;
391 &dpll_state[pll->index].hw_state,
396 pll->info->name,
397 dpll_state[pll->index].pipe_mask,
398 pll->active_mask);
399 return pll;
417 * @pll: DPLL for which the reference is taken
420 * Take a reference for @pll tracking the use of it by @crtc.
424 const struct intel_dpll *pll,
434 crtc->base.base.id, crtc->base.name, pll->info->name);
440 const struct intel_dpll *pll,
447 if (dpll_state[pll->index].pipe_mask == 0)
448 dpll_state[pll->index].hw_state = *dpll_hw_state;
450 intel_dpll_crtc_get(crtc, pll, &dpll_state[pll->index]);
456 * @pll: DPLL for which the reference is dropped
459 * Drop a reference for @pll tracking the end of use of it by @crtc.
463 const struct intel_dpll *pll,
473 crtc->base.base.id, crtc->base.name, pll->info->name);
478 const struct intel_dpll *pll)
484 intel_dpll_crtc_put(crtc, pll, &dpll_state[pll->index]);
518 struct intel_dpll *pll;
524 for_each_dpll(display, pll, i)
525 swap(pll->state, dpll_state[pll->index]);
529 struct intel_dpll *pll,
533 const enum intel_dpll_id id = pll->info->id;
565 struct intel_dpll *pll,
569 const enum intel_dpll_id id = pll->info->id;
594 struct intel_dpll *pll)
596 const enum intel_dpll_id id = pll->info->id;
617 struct intel_dpll *pll;
623 pll = intel_get_dpll_by_id(display, id);
628 pll->info->name);
630 pll = intel_find_dpll(state, crtc,
636 if (!pll)
639 /* reference the pll */
641 pll, &crtc_state->dpll_hw_state);
643 crtc_state->intel_dpll = pll;
695 struct intel_dpll *pll,
699 const enum intel_dpll_id id = pll->info->id;
707 struct intel_dpll *pll,
718 struct intel_dpll *pll)
720 const enum intel_dpll_id id = pll->info->id;
734 struct intel_dpll *pll)
736 enum intel_dpll_id id = pll->info->id;
750 struct intel_dpll *pll,
754 const enum intel_dpll_id id = pll->info->id;
772 struct intel_dpll *pll,
999 const struct intel_dpll *pll,
1097 struct intel_dpll *pll;
1116 pll = intel_get_dpll_by_id(display, pll_id);
1118 if (!pll)
1121 return pll;
1125 const struct intel_dpll *pll,
1130 switch (pll->info->id) {
1177 const struct intel_dpll *pll,
1224 struct intel_dpll *pll = NULL;
1227 pll = hsw_ddi_wrpll_get_dpll(state, crtc);
1229 pll = hsw_ddi_lcpll_get_dpll(crtc_state);
1231 pll = hsw_ddi_spll_get_dpll(state, crtc);
1233 if (!pll)
1237 pll, &crtc_state->dpll_hw_state);
1239 crtc_state->intel_dpll = pll;
1288 struct intel_dpll *pll,
1294 struct intel_dpll *pll)
1299 struct intel_dpll *pll,
1339 /* this array is indexed by the *shared* pll id */
1367 struct intel_dpll *pll,
1370 const enum intel_dpll_id id = pll->info->id;
1381 struct intel_dpll *pll,
1386 const enum intel_dpll_id id = pll->info->id;
1388 skl_ddi_pll_write_ctrl1(display, pll, hw_state);
1403 struct intel_dpll *pll,
1408 skl_ddi_pll_write_ctrl1(display, pll, hw_state);
1412 struct intel_dpll *pll)
1415 const enum intel_dpll_id id = pll->info->id;
1423 struct intel_dpll *pll)
1428 struct intel_dpll *pll,
1433 const enum intel_dpll_id id = pll->info->id;
1466 struct intel_dpll *pll,
1471 const enum intel_dpll_id id = pll->info->id;
1739 const struct intel_dpll *pll,
1887 const struct intel_dpll *pll,
1942 struct intel_dpll *pll;
1945 pll = intel_find_dpll(state, crtc,
1949 pll = intel_find_dpll(state, crtc,
1954 if (!pll)
1958 pll, &crtc_state->dpll_hw_state);
1960 crtc_state->intel_dpll = pll;
1966 const struct intel_dpll *pll,
1972 * ctrl1 register is already shifted for each pll, just use 0 to get
1976 return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
1978 return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
2041 struct intel_dpll *pll,
2045 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2144 struct intel_dpll *pll)
2146 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2163 struct intel_dpll *pll,
2167 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2363 const struct intel_dpll *pll,
2432 struct intel_dpll *pll;
2437 pll = intel_get_dpll_by_id(display, id);
2440 crtc->base.base.id, crtc->base.name, pll->info->name);
2443 pll, &crtc_state->dpll_hw_state);
2445 crtc_state->intel_dpll = pll;
2758 const struct intel_dpll *pll,
2829 const struct intel_dpll *pll,
3202 const struct intel_dpll *pll,
3288 crtc_state->intel_dpll = port_dpll->pll;
3391 port_dpll->pll = intel_find_dpll(state, crtc,
3394 if (!port_dpll->pll)
3398 port_dpll->pll, &port_dpll->hw_state);
3455 port_dpll->pll = intel_find_dpll(state, crtc,
3458 if (!port_dpll->pll)
3461 port_dpll->pll, &port_dpll->hw_state);
3465 port_dpll->pll = intel_find_dpll(state, crtc,
3468 if (!port_dpll->pll) {
3473 port_dpll->pll, &port_dpll->hw_state);
3481 intel_unreference_dpll(state, crtc, port_dpll->pll);
3531 new_port_dpll->pll = NULL;
3533 if (!old_port_dpll->pll)
3536 intel_unreference_dpll(state, crtc, old_port_dpll->pll);
3541 struct intel_dpll *pll,
3545 const enum intel_dpll_id id = pll->info->id;
3551 i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
3608 struct intel_dpll *pll,
3612 const enum intel_dpll_id id = pll->info->id;
3623 val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
3680 struct intel_dpll *pll,
3685 const enum intel_dpll_id id = pll->info->id;
3741 struct intel_dpll *pll,
3744 i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
3746 return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
3750 struct intel_dpll *pll,
3753 return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
3757 struct intel_dpll *pll,
3760 const enum intel_dpll_id id = pll->info->id;
3799 struct intel_dpll *pll,
3802 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3842 struct intel_dpll *pll,
3845 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3907 struct intel_dpll *pll,
3918 pll->info->id);
3922 struct intel_dpll *pll,
3929 drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
3932 static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)
3937 pll->info->id != DPLL_ID_ICL_DPLL0)
3957 struct intel_dpll *pll,
3961 i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
3963 icl_pll_power_enable(display, pll, enable_reg);
3965 icl_dpll_write(display, pll, hw_state);
3973 icl_pll_enable(display, pll, enable_reg);
3975 adlp_cmtg_clock_gating_wa(display, pll);
3981 struct intel_dpll *pll,
3986 icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
3988 icl_dpll_write(display, pll, hw_state);
3996 icl_pll_enable(display, pll, TBT_PLL_ENABLE);
4002 struct intel_dpll *pll,
4006 i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
4008 icl_pll_power_enable(display, pll, enable_reg);
4011 dkl_pll_write(display, pll, hw_state);
4013 icl_mg_pll_write(display, pll, hw_state);
4021 icl_pll_enable(display, pll, enable_reg);
4027 struct intel_dpll *pll,
4042 drm_err(display->drm, "PLL %d locked\n", pll->info->id);
4054 pll->info->id);
4058 struct intel_dpll *pll)
4060 i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
4062 icl_pll_disable(display, pll, enable_reg);
4066 struct intel_dpll *pll)
4068 icl_pll_disable(display, pll, TBT_PLL_ENABLE);
4072 struct intel_dpll *pll)
4074 i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
4076 icl_pll_disable(display, pll, enable_reg);
4478 * @pll: DPLL for which to calculate the output frequency
4481 * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
4484 const struct intel_dpll *pll,
4487 if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
4490 return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
4496 * @pll: DPLL for which to calculate the output frequency
4499 * Read out @pll's hardware state into @dpll_hw_state.
4502 struct intel_dpll *pll,
4505 return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
4509 struct intel_dpll *pll)
4513 pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
4515 if (pll->on && pll->info->power_domain)
4516 pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
4518 pll->state.pipe_mask = 0;
4523 if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
4524 intel_dpll_crtc_get(crtc, pll, &pll->state);
4526 pll->active_mask = pll->state.pipe_mask;
4530 pll->info->name, pll->state.pipe_mask, pll->on);
4541 struct intel_dpll *pll;
4544 for_each_dpll(display, pll, i)
4545 readout_dpll_hw_state(display, pll);
4549 struct intel_dpll *pll)
4551 if (!pll->on)
4554 adlp_cmtg_clock_gating_wa(display, pll);
4556 if (pll->active_mask)
4561 pll->info->name);
4563 _intel_disable_shared_dpll(display, pll);
4568 struct intel_dpll *pll;
4573 for_each_dpll(display, pll, i)
4574 sanitize_dpll_state(display, pll);
4625 struct intel_dpll *pll,
4633 active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
4635 if (!pll->info->always_on) {
4636 INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
4637 "%s: pll in active use but not on in sw tracking\n",
4638 pll->info->name);
4639 INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,
4640 "%s: pll is on but not used by any active pipe\n",
4641 pll->info->name);
4642 INTEL_DISPLAY_STATE_WARN(display, pll->on != active,
4643 "%s: pll on state mismatch (expected %i, found %i)\n",
4644 pll->info->name, pll->on, active);
4649 pll->active_mask & ~pll->state.pipe_mask,
4650 "%s: more active pll users than references: 0x%x vs 0x%x\n",
4651 pll->info->name, pll->active_mask, pll->state.pipe_mask);
4659 INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),
4660 "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
4661 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4663 INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
4664 "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
4665 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4667 INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),
4668 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
4669 pll->info->name, pipe_mask, pll->state.pipe_mask);
4672 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4674 "%s: pll hw state mismatch\n",
4675 pll->info->name);
4701 struct intel_dpll *pll = old_crtc_state->intel_dpll;
4703 INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
4704 "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4705 pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4710 pll->state.pipe_mask & pipe_mask,
4711 "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
4712 pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
4719 struct intel_dpll *pll;
4722 for_each_dpll(display, pll, i)
4723 verify_single_dpll_state(display, pll, NULL, NULL);