Lines Matching refs:dev_priv
392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
395 if (DISPLAY_VER(dev_priv) >= 4) {
399 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
400 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
402 tmp = intel_de_read(dev_priv,
403 DPLL_MD(dev_priv, crtc->pipe));
408 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe));
410 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
411 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
412 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe));
425 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
439 if (IS_PINEVIEW(dev_priv)) {
447 if (DISPLAY_VER(dev_priv) != 2) {
448 if (IS_PINEVIEW(dev_priv))
465 drm_dbg_kms(&dev_priv->drm,
471 if (IS_PINEVIEW(dev_priv))
478 if (IS_I85X(dev_priv) &&
479 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
481 u32 lvds = intel_de_read(dev_priv, LVDS);
517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
529 vlv_dpio_get(dev_priv);
530 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
531 vlv_dpio_put(dev_priv);
545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
557 vlv_dpio_get(dev_priv);
558 cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch));
559 pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch));
560 pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch));
561 pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch));
562 pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
563 vlv_dpio_put(dev_priv);
580 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
593 if (!IS_PINEVIEW(dev_priv) &&
594 !IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
595 !IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))
599 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
600 !IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
623 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
631 if (intel_is_dual_link_lvds(dev_priv))
1009 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1019 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1020 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1033 if (IS_G4X(dev_priv)) {
1036 } else if (IS_PINEVIEW(dev_priv)) {
1060 if (DISPLAY_VER(dev_priv) >= 4)
1079 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1082 if (IS_PINEVIEW(dev_priv)) {
1092 if (DISPLAY_VER(dev_priv) >= 4)
1102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1132 if (IS_I830(dev_priv) ||
1160 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1167 if (DISPLAY_VER(dev_priv) < 11 &&
1189 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1195 if (DISPLAY_VER(dev_priv) < 11 &&
1280 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1314 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1365 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1378 drm_dbg_kms(&dev_priv->drm,
1380 dev_priv->display.vbt.lvds_ssc_freq);
1381 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1384 if (intel_is_dual_link_lvds(dev_priv)) {
1542 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1550 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1551 drm_dbg_kms(&dev_priv->drm,
1556 if (intel_is_dual_link_lvds(dev_priv))
1592 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1600 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1601 drm_dbg_kms(&dev_priv->drm,
1631 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1639 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1640 drm_dbg_kms(&dev_priv->drm,
1672 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1680 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1681 drm_dbg_kms(&dev_priv->drm,
1805 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1807 if (DISPLAY_VER(dev_priv) >= 14)
1808 dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
1809 else if (IS_DG2(dev_priv))
1810 dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
1811 else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
1812 dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
1813 else if (HAS_PCH_SPLIT(dev_priv))
1814 dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
1815 else if (IS_CHERRYVIEW(dev_priv))
1816 dev_priv->display.funcs.dpll = &chv_dpll_funcs;
1817 else if (IS_VALLEYVIEW(dev_priv))
1818 dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
1819 else if (IS_G4X(dev_priv))
1820 dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
1821 else if (IS_PINEVIEW(dev_priv))
1822 dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
1823 else if (DISPLAY_VER(dev_priv) != 2)
1824 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
1826 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
1829 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1831 if (IS_I830(dev_priv))
1834 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1849 if (i9xx_has_pps(dev_priv))
1852 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0);
1853 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1);
1860 intel_de_write(dev_priv, DPLL(dev_priv, pipe),
1862 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
1865 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
1868 if (DISPLAY_VER(dev_priv) >= 4) {
1869 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
1877 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
1882 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
1883 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
1888 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
1897 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
1900 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
1902 tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
1905 vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
1907 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
1909 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
1911 tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
1914 vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
1920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1927 vlv_dpio_get(dev_priv);
1933 vlv_pllb_recal_opamp(dev_priv, phy, ch);
1936 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
1939 tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch));
1941 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp);
1944 vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
1960 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
1963 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
1969 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
1972 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
1978 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1981 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1986 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1989 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
1993 coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch));
1997 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk);
1999 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000);
2001 vlv_dpio_put(dev_priv);
2007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2011 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
2012 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
2015 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
2016 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
2023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2033 intel_de_write(dev_priv, DPLL(dev_priv, pipe),
2041 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md);
2042 intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
2048 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2057 vlv_dpio_get(dev_priv);
2060 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch),
2067 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch),
2071 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch),
2076 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch),
2080 tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
2085 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp);
2088 tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch));
2094 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp);
2119 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter);
2121 tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch));
2124 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp);
2127 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch),
2128 vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) |
2131 vlv_dpio_put(dev_priv);
2137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2144 vlv_dpio_get(dev_priv);
2147 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
2149 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp);
2151 vlv_dpio_put(dev_priv);
2159 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
2162 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
2163 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
2170 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2180 intel_de_write(dev_priv, DPLL(dev_priv, pipe),
2195 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
2196 intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B),
2198 intel_de_write(dev_priv, CBR4_VLV, 0);
2199 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
2205 drm_WARN_ON(&dev_priv->drm,
2206 (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
2209 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
2211 intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
2217 * @dev_priv: i915 private structure
2225 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
2228 struct intel_display *display = &dev_priv->display;
2241 if (IS_CHERRYVIEW(dev_priv)) {
2254 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2256 struct intel_display *display = &dev_priv->display;
2271 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2273 struct intel_display *display = &dev_priv->display;
2289 vlv_dpio_get(dev_priv);
2292 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
2294 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val);
2296 vlv_dpio_put(dev_priv);
2319 * @dev_priv: i915 private structure
2325 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
2327 if (IS_CHERRYVIEW(dev_priv))
2328 chv_disable_pll(dev_priv, pipe);
2330 vlv_disable_pll(dev_priv, pipe);